343 lines
8.1 KiB
Plaintext
343 lines
8.1 KiB
Plaintext
--- Test 1: read verilog with preproc and params ---
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cells: 10
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nets: 15
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ports: 9
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hierarchical cells: 13
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PASS: read verilog with preproc/param
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--- Test 2: timing ---
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v d2 (in)
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0.07 0.07 v ps1/g1/ZN (AND2_X1)
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0.03 0.09 v buf1/Z (BUF_X1)
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0.05 0.14 v or1/ZN (OR2_X1)
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0.00 0.14 v reg3/D (DFF_X1)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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9.82 slack (MET)
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PASS: report_checks
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg4 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ d2 (in)
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0.05 0.05 ^ ps1/g1/ZN (AND2_X1)
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0.00 0.05 ^ reg4/D (DFF_X1)
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0.05 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg4/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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0.04 slack (MET)
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PASS: min path
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No paths found.
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PASS: d1->q1
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No paths found.
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PASS: d3->q2
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No paths found.
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PASS: d1->q3 (through param_sub)
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Warning: verilog_preproc_param.tcl line 1, unknown field nets.
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 0.89 0.10 0.00 0.00 v d2 (in)
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0.10 0.00 0.00 v ps1/g1/A2 (AND2_X1)
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2 1.94 0.01 0.07 0.07 v ps1/g1/ZN (AND2_X1)
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0.01 0.00 0.07 v buf1/A (BUF_X1)
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2 1.96 0.01 0.03 0.09 v buf1/Z (BUF_X1)
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0.01 0.00 0.09 v or1/A2 (OR2_X1)
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1 1.06 0.01 0.05 0.14 v or1/ZN (OR2_X1)
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0.01 0.00 0.14 v reg3/D (DFF_X1)
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0.14 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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-----------------------------------------------------------------------------
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9.96 data required time
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-0.14 data arrival time
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-----------------------------------------------------------------------------
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9.82 slack (MET)
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PASS: report with fields
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--- Test 3: write ---
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PASS: write_verilog
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PASS: write_verilog -include_pwr_gnd
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PASS: output file non-empty size=864
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--- Test 4: reports ---
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Instance buf1
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input n1
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Output pins:
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Z output n4
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance inv1
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Cell: INV_X1
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Library: NangateOpenCellLibrary
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Path cells: INV_X1
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Input pins:
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A input n2
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Output pins:
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ZN output n5
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance or1
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Cell: OR2_X1
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Library: NangateOpenCellLibrary
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Path cells: OR2_X1
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Input pins:
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A1 input n3
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A2 input n4
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Output pins:
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ZN output n6
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg1
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n4
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CK input clk
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Output pins:
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Q output q1
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg2
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n5
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CK input clk
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Output pins:
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Q output q2
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg3
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n6
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CK input clk
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Output pins:
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Q output q3
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg4
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n1
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CK input clk
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Output pins:
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Q output q4
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance ps1
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Cell: param_sub
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Library: verilog
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Path cells: param_sub
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Input pins:
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A input d1
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B input d2
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Output pins:
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Y output n1
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Children:
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g1 (AND2_X1)
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Instance ps2
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Cell: param_sub
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Library: verilog
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Path cells: param_sub
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Input pins:
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A input d3
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B input d4
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Output pins:
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Y output n2
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Children:
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g1 (AND2_X1)
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Instance ps3
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Cell: param_sub
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Library: verilog
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Path cells: param_sub
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Input pins:
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A input d1
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B input d3
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Output pins:
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Y output n3
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Children:
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g1 (AND2_X1)
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PASS: instance reports
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Net n1
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Pin capacitance: 1.94-2.11
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Wire capacitance: 0.00
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Total capacitance: 1.94-2.11
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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ps1/g1/ZN output (AND2_X1)
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Load pins
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buf1/A input (BUF_X1) 0.88-0.97
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reg4/D input (DFF_X1) 1.06-1.14
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Hierarchical pins
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ps1/Y output
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Net n2
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Pin capacitance: 1.55-1.70
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Wire capacitance: 0.00
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Total capacitance: 1.55-1.70
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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ps2/g1/ZN output (AND2_X1)
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Load pins
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inv1/A input (INV_X1) 1.55-1.70
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Hierarchical pins
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ps2/Y output
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Net n3
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Pin capacitance: 0.79-0.95
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Wire capacitance: 0.00
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Total capacitance: 0.79-0.95
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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ps3/g1/ZN output (AND2_X1)
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Load pins
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or1/A1 input (OR2_X1) 0.79-0.95
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Hierarchical pins
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ps3/Y output
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Net n4
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Pin capacitance: 1.96-2.08
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Wire capacitance: 0.00
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Total capacitance: 1.96-2.08
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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or1/A2 input (OR2_X1) 0.90-0.94
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reg1/D input (DFF_X1) 1.06-1.14
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Net n5
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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inv1/ZN output (INV_X1)
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Load pins
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reg2/D input (DFF_X1) 1.06-1.14
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Net n6
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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or1/ZN output (OR2_X1)
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Load pins
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reg3/D input (DFF_X1) 1.06-1.14
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PASS: net reports
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--- Test 5: re-read ---
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Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
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re-read cells: 10
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PASS: re-read
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ALL PASSED
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