271 lines
11 KiB
Plaintext
271 lines
11 KiB
Plaintext
--- Test 1: Nangate examples ---
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PASS: link top (example1)
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cells: 5
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PASS: write default
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PASS: write -include_pwr_gnd
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Warning: verilog_multimodule_write.tcl line 1, The -sort flag is ignored.
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PASS: write -sort
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Warning: verilog_multimodule_write.tcl line 1, The -sort flag is ignored.
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PASS: write -include_pwr_gnd -sort
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/workspace/sta/OpenSTA/verilog/test/results/verilog_mm_default.v OK
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/workspace/sta/OpenSTA/verilog/test/results/verilog_mm_pwr.v OK
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/workspace/sta/OpenSTA/verilog/test/results/verilog_mm_sort.v OK
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/workspace/sta/OpenSTA/verilog/test/results/verilog_mm_pwr_sort.v OK
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PASS: output files
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--- Test 2: re-read default ---
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Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
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re-read cells: 5
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PASS: re-read default
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--- Test 3: re-read pwr ---
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Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
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re-read pwr cells: 5
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PASS: re-read pwr
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--- Test 4: timing after re-read ---
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CK (DFF_X1)
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0.08 0.08 v r2/Q (DFF_X1)
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0.02 0.10 v u1/Z (BUF_X1)
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0.03 0.13 v u2/ZN (AND2_X1)
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0.00 0.13 v r3/D (DFF_X1)
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0.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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9.83 slack (MET)
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PASS: report_checks
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Startpoint: in1 (input port clocked by clk)
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Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.00 0.00 v r1/D (DFF_X1)
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0.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ r1/CK (DFF_X1)
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0.05 0.05 library hold time
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0.05 data required time
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---------------------------------------------------------
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0.05 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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-0.05 slack (VIOLATED)
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PASS: min path
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Warning: verilog_multimodule_write.tcl line 1, unknown field nets.
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ r2/CK (DFF_X1)
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1 0.88 0.01 0.08 0.08 v r2/Q (DFF_X1)
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0.01 0.00 0.08 v u1/A (BUF_X1)
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1 0.89 0.00 0.02 0.10 v u1/Z (BUF_X1)
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0.00 0.00 0.10 v u2/A2 (AND2_X1)
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1 1.06 0.01 0.03 0.13 v u2/ZN (AND2_X1)
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0.01 0.00 0.13 v r3/D (DFF_X1)
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0.13 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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-----------------------------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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-----------------------------------------------------------------------------
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9.83 slack (MET)
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PASS: fields
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--- Test 5: queries ---
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r1 ref=DFF_X1
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r2 ref=DFF_X1
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r3 ref=DFF_X1
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u1 ref=BUF_X1
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u2 ref=AND2_X1
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PASS: instance queries
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Net r1q
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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r1/Q output (DFF_X1)
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Load pins
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u2/A1 input (AND2_X1) 0.87-0.92
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Net r2q
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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r2/Q output (DFF_X1)
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Load pins
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u1/A input (BUF_X1) 0.88-0.97
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Net u1z
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Pin capacitance: 0.89-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.89-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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u1/Z output (BUF_X1)
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Load pins
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u2/A2 input (AND2_X1) 0.89-0.97
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Net u2z
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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u2/ZN output (AND2_X1)
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Load pins
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r3/D input (DFF_X1) 1.06-1.14
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PASS: net queries
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--- Test 6: sorted re-read ---
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Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
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sorted cells: 5
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CK (DFF_X1)
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0.08 0.08 v r2/Q (DFF_X1)
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0.02 0.10 v u1/Z (BUF_X1)
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0.03 0.13 v u2/ZN (AND2_X1)
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0.00 0.13 v r3/D (DFF_X1)
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0.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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9.83 slack (MET)
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PASS: sorted re-read timing
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--- Test 7: ASAP7 design ---
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
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PASS: link reg1_asap7
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PASS: write ASAP7
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PASS: write ASAP7 -include_pwr_gnd
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Warning: ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib line 35, library asap7sc7p5t_SEQ_RVT_FF_nldm_220123 already exists.
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Warning: ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz line 34, library asap7sc7p5t_INVBUF_RVT_FF_nldm_211120 already exists.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 34, library asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120 already exists.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz line 34, library asap7sc7p5t_OA_RVT_FF_nldm_211120 already exists.
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Warning: ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz line 34, library asap7sc7p5t_AO_RVT_FF_nldm_211120 already exists.
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re-read ASAP7 cells: 5
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PASS: re-read ASAP7
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Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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0.04 0.04 ^ r3/Q (DFFHQx4_ASAP7_75t_R)
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0.00 0.04 ^ out (out)
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0.04 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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-1.00 499.00 output external delay
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499.00 data required time
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---------------------------------------------------------
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499.00 data required time
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-0.04 data arrival time
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---------------------------------------------------------
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498.96 slack (MET)
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PASS: ASAP7 timing
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ALL PASSED
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