158 lines
7.3 KiB
Plaintext
158 lines
7.3 KiB
Plaintext
--- Test 1: read GCD sky130hd ---
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Warning: ../../examples/gcd_sky130hd.v line 527, module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for TAP_11.
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cells: 1292
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nets: 288
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ports: 54
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req_msg* ports: 32
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resp_msg* ports: 16
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clk dir=input
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reset dir=input
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req_val dir=input
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req_rdy dir=output
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resp_val dir=output
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resp_rdy dir=input
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--- Test 2: write_verilog basic ---
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PASS: basic write_verilog size=74836
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--- Test 3: write_verilog -include_pwr_gnd ---
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PASS: pwr_gnd write_verilog size=74836
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PASS: pwr_gnd output >= basic output
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--- Test 4: write_verilog -remove_cells ---
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PASS: remove_cells write_verilog size=74836
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--- Test 5: read back written verilog ---
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Warning: ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.
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roundtrip cells: 1292
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roundtrip nets: 288
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roundtrip ports: 54
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PASS: roundtrip write_verilog size=74836
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--- Test 6: timing with bus ports ---
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Warning: verilog_hier_write.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
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Startpoint: _414_ (rising edge-triggered flip-flop clocked by clk)
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Endpoint: _424_ (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ _414_/CLK (sky130_fd_sc_hd__dfxtp_4)
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0.31 0.31 v _414_/Q (sky130_fd_sc_hd__dfxtp_4)
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0.12 0.43 v _214_/Y (sky130_fd_sc_hd__nor2b_4)
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0.31 0.74 v _215_/X (sky130_fd_sc_hd__maj3_2)
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0.31 1.05 v _216_/X (sky130_fd_sc_hd__maj3_2)
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0.34 1.40 v _217_/X (sky130_fd_sc_hd__maj3_2)
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0.32 1.72 v _218_/X (sky130_fd_sc_hd__maj3_2)
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0.36 2.08 v _219_/X (sky130_fd_sc_hd__maj3_2)
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0.21 2.29 ^ _222_/Y (sky130_fd_sc_hd__o211ai_4)
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0.14 2.42 v _225_/Y (sky130_fd_sc_hd__a311oi_4)
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0.29 2.72 ^ _228_/Y (sky130_fd_sc_hd__o311ai_4)
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0.13 2.85 v _231_/Y (sky130_fd_sc_hd__a311oi_4)
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0.41 3.26 v _292_/X (sky130_fd_sc_hd__o311a_2)
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0.35 3.61 ^ _295_/Y (sky130_fd_sc_hd__o31ai_4)
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0.35 3.96 v _333_/X (sky130_fd_sc_hd__mux2_1)
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0.00 3.96 v _424_/D (sky130_fd_sc_hd__dfxtp_2)
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3.96 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ _424_/CLK (sky130_fd_sc_hd__dfxtp_2)
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-0.13 9.87 library setup time
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9.87 data required time
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---------------------------------------------------------
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9.87 data required time
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-3.96 data arrival time
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---------------------------------------------------------
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5.91 slack (MET)
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PASS: report_checks GCD
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Startpoint: reset (input port clocked by clk)
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Endpoint: _413_ (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ reset (in)
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0.03 0.03 v _283_/Y (sky130_fd_sc_hd__o22ai_1)
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0.00 0.03 v _413_/D (sky130_fd_sc_hd__dfxtp_4)
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0.03 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ _413_/CLK (sky130_fd_sc_hd__dfxtp_4)
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-0.05 -0.05 library hold time
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-0.05 data required time
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---------------------------------------------------------
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-0.05 data required time
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-0.03 data arrival time
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---------------------------------------------------------
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0.08 slack (MET)
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PASS: report_checks min GCD
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Warning: verilog_hier_write.tcl line 1, unknown field nets.
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Startpoint: _414_ (rising edge-triggered flip-flop clocked by clk)
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Endpoint: _424_ (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ _414_/CLK (sky130_fd_sc_hd__dfxtp_4)
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3 0.01 0.03 0.31 0.31 v _414_/Q (sky130_fd_sc_hd__dfxtp_4)
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0.03 0.00 0.31 v _214_/B_N (sky130_fd_sc_hd__nor2b_4)
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2 0.01 0.04 0.12 0.43 v _214_/Y (sky130_fd_sc_hd__nor2b_4)
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0.04 0.00 0.43 v _215_/C (sky130_fd_sc_hd__maj3_2)
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2 0.01 0.06 0.31 0.74 v _215_/X (sky130_fd_sc_hd__maj3_2)
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0.06 0.00 0.74 v _216_/C (sky130_fd_sc_hd__maj3_2)
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2 0.01 0.06 0.31 1.05 v _216_/X (sky130_fd_sc_hd__maj3_2)
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0.06 0.00 1.05 v _217_/C (sky130_fd_sc_hd__maj3_2)
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2 0.01 0.08 0.34 1.40 v _217_/X (sky130_fd_sc_hd__maj3_2)
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0.08 0.00 1.40 v _218_/C (sky130_fd_sc_hd__maj3_2)
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2 0.01 0.06 0.32 1.72 v _218_/X (sky130_fd_sc_hd__maj3_2)
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0.06 0.00 1.72 v _219_/C (sky130_fd_sc_hd__maj3_2)
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3 0.02 0.10 0.36 2.08 v _219_/X (sky130_fd_sc_hd__maj3_2)
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0.10 0.00 2.08 v _222_/A2 (sky130_fd_sc_hd__o211ai_4)
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3 0.01 0.19 0.21 2.29 ^ _222_/Y (sky130_fd_sc_hd__o211ai_4)
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0.19 0.00 2.29 ^ _225_/A3 (sky130_fd_sc_hd__a311oi_4)
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4 0.01 0.13 0.14 2.42 v _225_/Y (sky130_fd_sc_hd__a311oi_4)
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0.13 0.00 2.42 v _228_/A3 (sky130_fd_sc_hd__o311ai_4)
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3 0.01 0.29 0.29 2.72 ^ _228_/Y (sky130_fd_sc_hd__o311ai_4)
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0.29 0.00 2.72 ^ _231_/A3 (sky130_fd_sc_hd__a311oi_4)
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2 0.01 0.11 0.13 2.85 v _231_/Y (sky130_fd_sc_hd__a311oi_4)
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0.11 0.00 2.85 v _292_/A3 (sky130_fd_sc_hd__o311a_2)
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3 0.02 0.10 0.41 3.26 v _292_/X (sky130_fd_sc_hd__o311a_2)
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0.10 0.00 3.26 v _295_/A3 (sky130_fd_sc_hd__o31ai_4)
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11 0.03 0.39 0.35 3.61 ^ _295_/Y (sky130_fd_sc_hd__o31ai_4)
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0.39 0.00 3.61 ^ _333_/S (sky130_fd_sc_hd__mux2_1)
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1 0.00 0.05 0.35 3.96 v _333_/X (sky130_fd_sc_hd__mux2_1)
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0.05 0.00 3.96 v _424_/D (sky130_fd_sc_hd__dfxtp_2)
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3.96 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ _424_/CLK (sky130_fd_sc_hd__dfxtp_2)
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-0.13 9.87 library setup time
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9.87 data required time
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-----------------------------------------------------------------------------
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9.87 data required time
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-3.96 data arrival time
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-----------------------------------------------------------------------------
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5.91 slack (MET)
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PASS: report_checks with fields GCD
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--- Test 7: write after timing setup ---
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PASS: post-timing write_verilog size=74836
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PASS: post-timing pwr write_verilog size=74836
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ALL PASSED
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