159 lines
4.9 KiB
Tcl
159 lines
4.9 KiB
Tcl
# Test VerilogReader with the larger GCD design which has more diverse
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# constructs: bus ports, bus nets, many instances, and complex connectivity.
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# Then write verilog with various options and re-read.
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# Targets:
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# VerilogReader.cc: readVerilog (large file), makeModule, makeModuleInst,
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# makeDcl, makeDclArg, makeDclBus, makeNetConcat,
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# linkNetwork, checkModule, resolveModule, linkModuleInst,
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# linkWire, VerilogNet, VerilogDcl, VerilogDclBus,
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# bus port parsing, bus net connections,
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# VerilogError reporting for missing modules
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# VerilogWriter.cc: writeVerilog, writeModule, writeInstance,
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# writeNet, writeBus, writePowerGround, writeSort,
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# -remove_cells, -include_pwr_gnd, -sort
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# VerilogLex.ll: tokenization of larger file, bus brackets,
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# escaped identifiers, string tokens
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source ../../test/helpers.tcl
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############################################################
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# Test 1: Read Sky130 library and GCD verilog
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############################################################
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puts "--- Test 1: read GCD design ---"
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read_liberty ../../test/sky130hd/sky130hd_tt.lib
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read_verilog ../../examples/gcd_sky130hd.v
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link_design gcd
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puts "PASS: link gcd"
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Verify bus ports are parsed correctly
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foreach port_pattern {req_msg resp_msg} {
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set bus_ports [get_ports $port_pattern*]
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puts "bus $port_pattern: [llength $bus_ports] bits"
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}
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puts "PASS: bus ports"
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############################################################
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# Test 2: Write verilog with various options
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############################################################
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puts "--- Test 2: write verilog ---"
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set out1 [make_result_file verilog_gcd_large_out.v]
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write_verilog $out1
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puts "PASS: write_verilog"
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set out2 [make_result_file verilog_gcd_large_pwr.v]
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write_verilog -include_pwr_gnd $out2
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puts "PASS: write_verilog -include_pwr_gnd"
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set out3 [make_result_file verilog_gcd_large_sort.v]
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write_verilog -sort $out3
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puts "PASS: write_verilog -sort"
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# Verify files are non-empty
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foreach outf [list $out1 $out2 $out3] {
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if {[file exists $outf] && [file size $outf] > 0} {
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puts " $outf size=[file size $outf]"
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} else {
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puts " WARNING: $outf missing or empty"
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}
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}
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puts "PASS: output files"
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############################################################
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# Test 3: Re-read written verilog
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############################################################
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puts "--- Test 3: re-read ---"
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read_liberty ../../test/sky130hd/sky130hd_tt.lib
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read_verilog $out1
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link_design gcd
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puts "re-read cells: [llength [get_cells *]]"
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puts "PASS: re-read"
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############################################################
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# Test 4: Timing with the design
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############################################################
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puts "--- Test 4: timing ---"
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source ../../examples/gcd_sky130hd.sdc
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report_checks -endpoint_count 3
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puts "PASS: report_checks"
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report_checks -path_delay min -endpoint_count 3
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puts "PASS: min path"
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report_checks -fields {slew cap input_pins nets fanout}
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puts "PASS: fields"
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report_checks -format full_clock
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puts "PASS: full_clock"
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############################################################
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# Test 5: Write with -remove_cells to exclude specific cells
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############################################################
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puts "--- Test 5: write with remove ---"
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set out4 [make_result_file verilog_gcd_large_remove.v]
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catch {
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write_verilog -remove_cells {sky130_fd_sc_hd__fill_1 sky130_fd_sc_hd__fill_2} $out4
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puts "PASS: write_verilog -remove_cells"
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} msg
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if {[string match "*Error*" $msg]} {
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# If -remove_cells is not supported, try without it
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write_verilog $out4
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puts "PASS: write_verilog fallback"
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}
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############################################################
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# Test 6: Instance and net reports
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############################################################
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puts "--- Test 6: instance/net reports ---"
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set inst_count 0
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foreach inst_obj [get_cells *] {
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catch {report_instance [get_name $inst_obj]}
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incr inst_count
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if {$inst_count >= 20} break
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}
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puts "PASS: instance reports ($inst_count)"
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set net_count 0
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foreach net_obj [get_nets *] {
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catch {report_net [get_name $net_obj]}
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incr net_count
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if {$net_count >= 20} break
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}
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puts "PASS: net reports ($net_count)"
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############################################################
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# Test 7: Read and write the example1 design too
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############################################################
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puts "--- Test 7: example1 ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog ../../examples/example1.v
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link_design top
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puts "PASS: link example1"
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set out5 [make_result_file verilog_example1_out.v]
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write_verilog $out5
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puts "PASS: write example1"
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# Re-read
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out5
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link_design top
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puts "PASS: re-read example1"
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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report_checks
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puts "PASS: timing example1"
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puts "ALL PASSED"
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