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OpenSTA/verilog/test/verilog_gcd_large.ok

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--- Test 1: read GCD design ---
Warning: ../../examples/gcd_sky130hd.v line 527, module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for TAP_11.
PASS: link gcd
cells: 1292
nets: 288
ports: 54
bus req_msg: 32 bits
bus resp_msg: 16 bits
PASS: bus ports
--- Test 2: write verilog ---
PASS: write_verilog
PASS: write_verilog -include_pwr_gnd
Warning: verilog_gcd_large.tcl line 1, The -sort flag is ignored.
PASS: write_verilog -sort
/workspace/sta/OpenSTA/verilog/test/results/verilog_gcd_large_out.v size=74836
/workspace/sta/OpenSTA/verilog/test/results/verilog_gcd_large_pwr.v size=74836
/workspace/sta/OpenSTA/verilog/test/results/verilog_gcd_large_sort.v size=74836
PASS: output files
--- Test 3: re-read ---
Warning: ../../test/sky130hd/sky130hd_tt.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.
re-read cells: 1292
PASS: re-read
--- Test 4: timing ---
Warning: verilog_gcd_large.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
Startpoint: _414_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: resp_msg[15] (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _414_/CLK (sky130_fd_sc_hd__dfxtp_4)
0.31 0.31 v _414_/Q (sky130_fd_sc_hd__dfxtp_4)
0.12 0.43 v _214_/Y (sky130_fd_sc_hd__nor2b_4)
0.31 0.74 v _215_/X (sky130_fd_sc_hd__maj3_2)
0.31 1.05 v _216_/X (sky130_fd_sc_hd__maj3_2)
0.34 1.40 v _217_/X (sky130_fd_sc_hd__maj3_2)
0.32 1.72 v _218_/X (sky130_fd_sc_hd__maj3_2)
0.36 2.08 v _219_/X (sky130_fd_sc_hd__maj3_2)
0.21 2.29 ^ _222_/Y (sky130_fd_sc_hd__o211ai_4)
0.14 2.42 v _225_/Y (sky130_fd_sc_hd__a311oi_4)
0.29 2.72 ^ _228_/Y (sky130_fd_sc_hd__o311ai_4)
0.13 2.85 v _231_/Y (sky130_fd_sc_hd__a311oi_4)
0.17 3.03 ^ _232_/Y (sky130_fd_sc_hd__nor2_2)
0.10 3.12 v _234_/Y (sky130_fd_sc_hd__a21boi_2)
0.12 3.25 v _238_/Y (sky130_fd_sc_hd__xnor2_2)
0.00 3.25 v resp_msg[15] (out)
3.25 data arrival time
5.00 5.00 clock clk (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
-1.00 4.00 output external delay
4.00 data required time
---------------------------------------------------------
4.00 data required time
-3.25 data arrival time
---------------------------------------------------------
0.75 slack (MET)
Startpoint: _414_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: resp_msg[15] (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _414_/CLK (sky130_fd_sc_hd__dfxtp_4)
0.31 0.31 v _414_/Q (sky130_fd_sc_hd__dfxtp_4)
0.12 0.43 v _214_/Y (sky130_fd_sc_hd__nor2b_4)
0.31 0.74 v _215_/X (sky130_fd_sc_hd__maj3_2)
0.31 1.05 v _216_/X (sky130_fd_sc_hd__maj3_2)
0.34 1.40 v _217_/X (sky130_fd_sc_hd__maj3_2)
0.32 1.72 v _218_/X (sky130_fd_sc_hd__maj3_2)
0.36 2.08 v _219_/X (sky130_fd_sc_hd__maj3_2)
0.21 2.29 ^ _222_/Y (sky130_fd_sc_hd__o211ai_4)
0.14 2.42 v _225_/Y (sky130_fd_sc_hd__a311oi_4)
0.29 2.72 ^ _228_/Y (sky130_fd_sc_hd__o311ai_4)
0.13 2.85 v _231_/Y (sky130_fd_sc_hd__a311oi_4)
0.17 3.03 ^ _232_/Y (sky130_fd_sc_hd__nor2_2)
0.10 3.12 v _234_/Y (sky130_fd_sc_hd__a21boi_2)
0.12 3.24 ^ _238_/Y (sky130_fd_sc_hd__xnor2_2)
0.00 3.24 ^ resp_msg[15] (out)
3.24 data arrival time
5.00 5.00 clock clk (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
-1.00 4.00 output external delay
4.00 data required time
---------------------------------------------------------
4.00 data required time
-3.24 data arrival time
---------------------------------------------------------
0.76 slack (MET)
Startpoint: _414_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: resp_msg[13] (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _414_/CLK (sky130_fd_sc_hd__dfxtp_4)
0.31 0.31 v _414_/Q (sky130_fd_sc_hd__dfxtp_4)
0.12 0.43 v _214_/Y (sky130_fd_sc_hd__nor2b_4)
0.31 0.74 v _215_/X (sky130_fd_sc_hd__maj3_2)
0.31 1.05 v _216_/X (sky130_fd_sc_hd__maj3_2)
0.34 1.40 v _217_/X (sky130_fd_sc_hd__maj3_2)
0.32 1.72 v _218_/X (sky130_fd_sc_hd__maj3_2)
0.36 2.08 v _219_/X (sky130_fd_sc_hd__maj3_2)
0.21 2.29 ^ _222_/Y (sky130_fd_sc_hd__o211ai_4)
0.14 2.42 v _225_/Y (sky130_fd_sc_hd__a311oi_4)
0.29 2.72 ^ _228_/Y (sky130_fd_sc_hd__o311ai_4)
0.25 2.97 ^ rebuffer2/X (sky130_fd_sc_hd__dlygate4sd1_1)
0.11 3.08 v _266_/Y (sky130_fd_sc_hd__a31oi_2)
0.16 3.24 ^ _268_/Y (sky130_fd_sc_hd__xnor2_2)
0.00 3.24 ^ resp_msg[13] (out)
3.24 data arrival time
5.00 5.00 clock clk (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
-1.00 4.00 output external delay
4.00 data required time
---------------------------------------------------------
4.00 data required time
-3.24 data arrival time
---------------------------------------------------------
0.76 slack (MET)
PASS: report_checks
Warning: verilog_gcd_large.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
Startpoint: _412_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _412_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _412_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.29 0.29 ^ _412_/Q (sky130_fd_sc_hd__dfxtp_1)
0.11 0.40 ^ _290_/X (sky130_fd_sc_hd__a32o_1)
0.00 0.40 ^ _412_/D (sky130_fd_sc_hd__dfxtp_1)
0.40 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _412_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.04 -0.04 library hold time
-0.04 data required time
---------------------------------------------------------
-0.04 data required time
-0.40 data arrival time
---------------------------------------------------------
0.43 slack (MET)
Startpoint: _424_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _440_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _424_/CLK (sky130_fd_sc_hd__dfxtp_2)
0.31 0.31 v _424_/Q (sky130_fd_sc_hd__dfxtp_2)
0.05 0.36 ^ _386_/Y (sky130_fd_sc_hd__nand2_1)
0.04 0.41 v _389_/Y (sky130_fd_sc_hd__a21oi_1)
0.00 0.41 v _440_/D (sky130_fd_sc_hd__dfxtp_1)
0.41 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _440_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.06 -0.06 library hold time
-0.06 data required time
---------------------------------------------------------
-0.06 data required time
-0.41 data arrival time
---------------------------------------------------------
0.46 slack (MET)
Startpoint: _419_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _419_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _419_/CLK (sky130_fd_sc_hd__dfxtp_2)
0.33 0.33 ^ _419_/Q (sky130_fd_sc_hd__dfxtp_2)
0.05 0.38 v _318_/Y (sky130_fd_sc_hd__nand2_1)
0.05 0.43 ^ _319_/Y (sky130_fd_sc_hd__o21ai_0)
0.00 0.43 ^ _419_/D (sky130_fd_sc_hd__dfxtp_2)
0.43 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _419_/CLK (sky130_fd_sc_hd__dfxtp_2)
-0.04 -0.04 library hold time
-0.04 data required time
---------------------------------------------------------
-0.04 data required time
-0.43 data arrival time
---------------------------------------------------------
0.47 slack (MET)
PASS: min path
Warning: verilog_gcd_large.tcl line 1, unknown field nets.
Startpoint: _414_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: resp_msg[15] (output port clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _414_/CLK (sky130_fd_sc_hd__dfxtp_4)
3 0.01 0.03 0.31 0.31 v _414_/Q (sky130_fd_sc_hd__dfxtp_4)
0.03 0.00 0.31 v _214_/B_N (sky130_fd_sc_hd__nor2b_4)
2 0.01 0.04 0.12 0.43 v _214_/Y (sky130_fd_sc_hd__nor2b_4)
0.04 0.00 0.43 v _215_/C (sky130_fd_sc_hd__maj3_2)
2 0.01 0.06 0.31 0.74 v _215_/X (sky130_fd_sc_hd__maj3_2)
0.06 0.00 0.74 v _216_/C (sky130_fd_sc_hd__maj3_2)
2 0.01 0.06 0.31 1.05 v _216_/X (sky130_fd_sc_hd__maj3_2)
0.06 0.00 1.05 v _217_/C (sky130_fd_sc_hd__maj3_2)
2 0.01 0.08 0.34 1.40 v _217_/X (sky130_fd_sc_hd__maj3_2)
0.08 0.00 1.40 v _218_/C (sky130_fd_sc_hd__maj3_2)
2 0.01 0.06 0.32 1.72 v _218_/X (sky130_fd_sc_hd__maj3_2)
0.06 0.00 1.72 v _219_/C (sky130_fd_sc_hd__maj3_2)
3 0.02 0.10 0.36 2.08 v _219_/X (sky130_fd_sc_hd__maj3_2)
0.10 0.00 2.08 v _222_/A2 (sky130_fd_sc_hd__o211ai_4)
3 0.01 0.19 0.21 2.29 ^ _222_/Y (sky130_fd_sc_hd__o211ai_4)
0.19 0.00 2.29 ^ _225_/A3 (sky130_fd_sc_hd__a311oi_4)
4 0.01 0.13 0.14 2.42 v _225_/Y (sky130_fd_sc_hd__a311oi_4)
0.13 0.00 2.42 v _228_/A3 (sky130_fd_sc_hd__o311ai_4)
3 0.01 0.29 0.29 2.72 ^ _228_/Y (sky130_fd_sc_hd__o311ai_4)
0.29 0.00 2.72 ^ _231_/A3 (sky130_fd_sc_hd__a311oi_4)
2 0.01 0.11 0.13 2.85 v _231_/Y (sky130_fd_sc_hd__a311oi_4)
0.11 0.00 2.85 v _232_/B (sky130_fd_sc_hd__nor2_2)
2 0.01 0.17 0.17 3.03 ^ _232_/Y (sky130_fd_sc_hd__nor2_2)
0.17 0.00 3.03 ^ _234_/A2 (sky130_fd_sc_hd__a21boi_2)
2 0.01 0.08 0.10 3.12 v _234_/Y (sky130_fd_sc_hd__a21boi_2)
0.08 0.00 3.12 v _238_/A (sky130_fd_sc_hd__xnor2_2)
1 0.00 0.04 0.12 3.25 v _238_/Y (sky130_fd_sc_hd__xnor2_2)
0.04 0.00 3.25 v resp_msg[15] (out)
3.25 data arrival time
0.00 5.00 5.00 clock clk (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
-1.00 4.00 output external delay
4.00 data required time
-----------------------------------------------------------------------------
4.00 data required time
-3.25 data arrival time
-----------------------------------------------------------------------------
0.75 slack (MET)
PASS: fields
Startpoint: _414_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: resp_msg[15] (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ _414_/CLK (sky130_fd_sc_hd__dfxtp_4)
0.31 0.31 v _414_/Q (sky130_fd_sc_hd__dfxtp_4)
0.12 0.43 v _214_/Y (sky130_fd_sc_hd__nor2b_4)
0.31 0.74 v _215_/X (sky130_fd_sc_hd__maj3_2)
0.31 1.05 v _216_/X (sky130_fd_sc_hd__maj3_2)
0.34 1.40 v _217_/X (sky130_fd_sc_hd__maj3_2)
0.32 1.72 v _218_/X (sky130_fd_sc_hd__maj3_2)
0.36 2.08 v _219_/X (sky130_fd_sc_hd__maj3_2)
0.21 2.29 ^ _222_/Y (sky130_fd_sc_hd__o211ai_4)
0.14 2.42 v _225_/Y (sky130_fd_sc_hd__a311oi_4)
0.29 2.72 ^ _228_/Y (sky130_fd_sc_hd__o311ai_4)
0.13 2.85 v _231_/Y (sky130_fd_sc_hd__a311oi_4)
0.17 3.03 ^ _232_/Y (sky130_fd_sc_hd__nor2_2)
0.10 3.12 v _234_/Y (sky130_fd_sc_hd__a21boi_2)
0.12 3.25 v _238_/Y (sky130_fd_sc_hd__xnor2_2)
0.00 3.25 v resp_msg[15] (out)
3.25 data arrival time
5.00 5.00 clock clk (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 clock reconvergence pessimism
-1.00 4.00 output external delay
4.00 data required time
---------------------------------------------------------
4.00 data required time
-3.25 data arrival time
---------------------------------------------------------
0.75 slack (MET)
PASS: full_clock
--- Test 5: write with remove ---
Warning: verilog_gcd_large.tcl line 1, object 'sky130_fd_sc_hd__fill_1' not found.
Warning: verilog_gcd_large.tcl line 1, object 'sky130_fd_sc_hd__fill_2' not found.
PASS: write_verilog -remove_cells
--- Test 6: instance/net reports ---
Instance TAP_0
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_10
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_100
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1000
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1001
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1002
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1003
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1004
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1005
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1006
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1007
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1008
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1009
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_101
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1010
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1011
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1012
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1013
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
Instance TAP_1014
Cell: sky130_fd_sc_hd__tapvpwrvgnd_1
Library: verilog
Path cells: sky130_fd_sc_hd__tapvpwrvgnd_1
Input pins:
Output pins:
PASS: instance reports (20)
Net _000_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_289_/Y output (sky130_fd_sc_hd__o21ai_0)
Load pins
_411_/D input (sky130_fd_sc_hd__dfxtp_4) 0.00-0.00
Net _001_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_290_/X output (sky130_fd_sc_hd__a32o_1)
Load pins
_412_/D input (sky130_fd_sc_hd__dfxtp_1) 0.00-0.00
Net _002_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_283_/Y output (sky130_fd_sc_hd__o22ai_1)
Load pins
_413_/D input (sky130_fd_sc_hd__dfxtp_4) 0.00-0.00
Net _003_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_302_/Y output (sky130_fd_sc_hd__nand2_1)
Load pins
_414_/D input (sky130_fd_sc_hd__dfxtp_4) 0.00-0.00
Net _004_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_305_/Y output (sky130_fd_sc_hd__nand2_1)
Load pins
_415_/D input (sky130_fd_sc_hd__dfxtp_1) 0.00-0.00
Net _005_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_309_/Y output (sky130_fd_sc_hd__nand2_1)
Load pins
_416_/D input (sky130_fd_sc_hd__dfxtp_1) 0.00-0.00
Net _006_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_312_/Y output (sky130_fd_sc_hd__nand2_1)
Load pins
_417_/D input (sky130_fd_sc_hd__dfxtp_2) 0.00-0.00
Net _007_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_316_/Y output (sky130_fd_sc_hd__a221oi_1)
Load pins
_418_/D input (sky130_fd_sc_hd__dfxtp_1) 0.00-0.00
Net _008_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_319_/Y output (sky130_fd_sc_hd__o21ai_0)
Load pins
_419_/D input (sky130_fd_sc_hd__dfxtp_2) 0.00-0.00
Net _009_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_322_/Y output (sky130_fd_sc_hd__nand2_1)
Load pins
_420_/D input (sky130_fd_sc_hd__dfxtp_2) 0.00-0.00
Net _010_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_325_/Y output (sky130_fd_sc_hd__nand2_1)
Load pins
_421_/D input (sky130_fd_sc_hd__dfxtp_1) 0.00-0.00
Net _011_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_328_/Y output (sky130_fd_sc_hd__o21ai_0)
Load pins
_422_/D input (sky130_fd_sc_hd__dfxtp_2) 0.00-0.00
Net _012_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_331_/Y output (sky130_fd_sc_hd__o21ai_0)
Load pins
_423_/D input (sky130_fd_sc_hd__dfxtp_1) 0.00-0.00
Net _013_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_333_/X output (sky130_fd_sc_hd__mux2_1)
Load pins
_424_/D input (sky130_fd_sc_hd__dfxtp_2) 0.00-0.00
Net _014_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_336_/Y output (sky130_fd_sc_hd__nand2_1)
Load pins
_425_/D input (sky130_fd_sc_hd__dfxtp_2) 0.00-0.00
Net _015_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_339_/Y output (sky130_fd_sc_hd__nand2_1)
Load pins
_426_/D input (sky130_fd_sc_hd__dfxtp_2) 0.00-0.00
Net _016_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_342_/Y output (sky130_fd_sc_hd__o21ai_0)
Load pins
_427_/D input (sky130_fd_sc_hd__dfxtp_1) 0.00-0.00
Net _017_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_345_/Y output (sky130_fd_sc_hd__nand2_1)
Load pins
_428_/D input (sky130_fd_sc_hd__dfxtp_1) 0.00-0.00
Net _018_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_348_/Y output (sky130_fd_sc_hd__nand2_1)
Load pins
_429_/D input (sky130_fd_sc_hd__dfxtp_1) 0.00-0.00
Net _019_
Pin capacitance: 0.00-0.00
Wire capacitance: 0.00
Total capacitance: 0.00-0.00
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
_355_/Y output (sky130_fd_sc_hd__a21oi_1)
Load pins
_430_/D input (sky130_fd_sc_hd__dfxtp_2) 0.00-0.00
PASS: net reports (20)
--- Test 7: example1 ---
PASS: link example1
PASS: write example1
Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
PASS: re-read example1
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ r2/CK (DFF_X1)
0.08 0.08 v r2/Q (DFF_X1)
0.02 0.10 v u1/Z (BUF_X1)
0.03 0.13 v u2/ZN (AND2_X1)
0.00 0.13 v r3/D (DFF_X1)
0.13 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ r3/CK (DFF_X1)
-0.04 9.96 library setup time
9.96 data required time
---------------------------------------------------------
9.96 data required time
-0.13 data arrival time
---------------------------------------------------------
9.83 slack (MET)
PASS: timing example1
ALL PASSED
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