262 lines
8.5 KiB
Tcl
262 lines
8.5 KiB
Tcl
# Test verilog writer with escaped names and bus wire declarations.
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# Targets:
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# VerilogWriter.cc: writeModule, writePorts, writePortDcls, writeWireDcls,
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# writeChildren, writeChild, writeInstPin, writeInstBusPin,
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# writeInstBusPinBit, writeAssigns, findUnconnectedNetCount,
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# findChildNCcount, findPortNCcount, verilogPortDir for all directions
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# VerilogNamespace.cc: staToVerilog (escaped names with special chars),
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# staToVerilog2 (bus bracket escaping), netVerilogName (bus net names),
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# portVerilogName, cellVerilogName, instanceVerilogName
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# VerilogReader.cc: reading back written files, escaped name parsing,
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# verilogToSta, moduleVerilogToSta, instanceVerilogToSta,
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# netVerilogToSta, portVerilogToSta
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 1: Write verilog for bus design (exercises bus wire declarations)
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#---------------------------------------------------------------
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puts "--- Test 1: write bus design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_bus_test.v
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link_design verilog_bus_test
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Write basic
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set out1 [make_result_file verilog_escaped_bus.v]
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write_verilog $out1
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puts "PASS: write_verilog bus design"
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if { [file exists $out1] && [file size $out1] > 0 } {
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puts "PASS: bus output size=[file size $out1]"
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}
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# Write with pwr_gnd
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set out2 [make_result_file verilog_escaped_bus_pwr.v]
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write_verilog -include_pwr_gnd $out2
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puts "PASS: write_verilog bus -include_pwr_gnd"
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if { [file exists $out2] && [file size $out2] > 0 } {
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puts "PASS: bus pwr output size=[file size $out2]"
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}
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# pwr_gnd should be larger
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set sz1 [file size $out1]
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set sz2 [file size $out2]
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if { $sz2 >= $sz1 } {
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puts "PASS: pwr_gnd >= basic"
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}
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#---------------------------------------------------------------
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# Test 2: Read back written bus verilog (roundtrip)
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# Exercises: verilogToSta on bus names, bus port parsing
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#---------------------------------------------------------------
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puts "--- Test 2: roundtrip bus design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out1
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link_design verilog_bus_test
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set rt_cells [get_cells *]
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puts "roundtrip cells: [llength $rt_cells]"
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set rt_nets [get_nets *]
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puts "roundtrip nets: [llength $rt_nets]"
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set rt_ports [get_ports *]
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puts "roundtrip ports: [llength $rt_ports]"
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# Verify bus ports after roundtrip
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set rt_din [get_ports {data_in[*]}]
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puts "roundtrip data_in[*]: [llength $rt_din]"
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set rt_dout [get_ports {data_out[*]}]
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puts "roundtrip data_out[*]: [llength $rt_dout]"
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# Timing after roundtrip
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {data_in[*]}]
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set_output_delay -clock clk 0 [get_ports {data_out[*]}]
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set_input_transition 0.1 [all_inputs]
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report_checks
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puts "PASS: timing after roundtrip"
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#---------------------------------------------------------------
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# Test 3: Write complex bus design
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# Exercises: writeWireDcls with bus nets (isBusName, parseBusName)
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#---------------------------------------------------------------
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puts "--- Test 3: write complex bus design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_complex_bus_test.v
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link_design verilog_complex_bus_test
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set out3 [make_result_file verilog_escaped_complex.v]
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write_verilog $out3
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puts "PASS: write_verilog complex bus"
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if { [file exists $out3] && [file size $out3] > 0 } {
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puts "PASS: complex output size=[file size $out3]"
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}
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set out4 [make_result_file verilog_escaped_complex_pwr.v]
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write_verilog -include_pwr_gnd $out4
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puts "PASS: write_verilog complex -include_pwr_gnd"
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if { [file exists $out4] && [file size $out4] > 0 } {
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puts "PASS: complex pwr output size=[file size $out4]"
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}
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# Read back complex bus design
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puts "--- roundtrip complex bus ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out3
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link_design verilog_complex_bus_test
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set rt2_cells [get_cells *]
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puts "complex roundtrip cells: [llength $rt2_cells]"
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set rt2_ports [get_ports *]
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puts "complex roundtrip ports: [llength $rt2_ports]"
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# Bus port queries after roundtrip
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set rt2_da [get_ports {data_a[*]}]
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puts "roundtrip data_a[*]: [llength $rt2_da]"
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set rt2_db [get_ports {data_b[*]}]
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puts "roundtrip data_b[*]: [llength $rt2_db]"
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set rt2_res [get_ports {result[*]}]
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puts "roundtrip result[*]: [llength $rt2_res]"
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# Timing after complex roundtrip
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {data_a[*]}]
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set_input_delay -clock clk 0 [get_ports {data_b[*]}]
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set_output_delay -clock clk 0 [get_ports {result[*]}]
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set_output_delay -clock clk 0 [get_ports carry]
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set_output_delay -clock clk 0 [get_ports overflow]
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set_input_transition 0.1 [all_inputs]
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report_checks
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puts "PASS: timing after complex roundtrip"
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#---------------------------------------------------------------
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# Test 4: Write hierarchical design
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# Exercises: findHierChildren, writeModule for sub-modules,
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# sorted child output
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#---------------------------------------------------------------
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puts "--- Test 4: write hierarchical design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog ../../network/test/network_hier_test.v
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link_design network_hier_test
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set out5 [make_result_file verilog_escaped_hier.v]
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write_verilog $out5
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puts "PASS: write_verilog hier"
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if { [file exists $out5] && [file size $out5] > 0 } {
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puts "PASS: hier output size=[file size $out5]"
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}
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set out6 [make_result_file verilog_escaped_hier_pwr.v]
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write_verilog -include_pwr_gnd $out6
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puts "PASS: write_verilog hier -include_pwr_gnd"
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if { [file exists $out6] && [file size $out6] > 0 } {
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puts "PASS: hier pwr output size=[file size $out6]"
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}
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# Roundtrip hierarchical
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out5
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link_design network_hier_test
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set rt3_cells [get_cells *]
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puts "hier roundtrip cells: [llength $rt3_cells]"
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set rt3_nets [get_nets *]
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puts "hier roundtrip nets: [llength $rt3_nets]"
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set rt3_ports [get_ports *]
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puts "hier roundtrip ports: [llength $rt3_ports]"
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# Timing after hierarchical roundtrip
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {in1 in2 in3}]
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set_output_delay -clock clk 0 [get_ports {out1 out2}]
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set_input_transition 0.1 [all_inputs]
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report_checks
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puts "PASS: timing after hier roundtrip"
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#---------------------------------------------------------------
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# Test 5: Write supply/tristate design (special port directions)
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# Exercises: verilogPortDir for tristate/supply, writePortDcls
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# tristate handling, writeAssigns for output aliases
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#---------------------------------------------------------------
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puts "--- Test 5: write supply/tristate design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_supply_tristate.v
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link_design verilog_supply_tristate
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set out7 [make_result_file verilog_escaped_supply.v]
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write_verilog $out7
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puts "PASS: write_verilog supply/tri"
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if { [file exists $out7] && [file size $out7] > 0 } {
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puts "PASS: supply output size=[file size $out7]"
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}
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set out8 [make_result_file verilog_escaped_supply_pwr.v]
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write_verilog -include_pwr_gnd $out8
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puts "PASS: write_verilog supply -include_pwr_gnd"
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if { [file exists $out8] && [file size $out8] > 0 } {
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puts "PASS: supply pwr output size=[file size $out8]"
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}
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#---------------------------------------------------------------
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# Test 6: Write constant/concat design
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# Exercises: writeChildren with constant pin connections
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#---------------------------------------------------------------
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puts "--- Test 6: write constant design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_const_concat.v
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link_design verilog_const_concat
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set out9 [make_result_file verilog_escaped_const.v]
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write_verilog $out9
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puts "PASS: write_verilog const/concat"
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if { [file exists $out9] && [file size $out9] > 0 } {
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puts "PASS: const output size=[file size $out9]"
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}
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set out10 [make_result_file verilog_escaped_const_pwr.v]
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write_verilog -include_pwr_gnd $out10
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puts "PASS: write_verilog const -include_pwr_gnd"
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if { [file exists $out10] && [file size $out10] > 0 } {
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puts "PASS: const pwr output size=[file size $out10]"
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}
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# Roundtrip constant design
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out9
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link_design verilog_const_concat
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set rt4_cells [get_cells *]
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puts "const roundtrip cells: [llength $rt4_cells]"
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set rt4_nets [get_nets *]
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puts "const roundtrip nets: [llength $rt4_nets]"
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puts "PASS: const roundtrip"
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puts "ALL PASSED"
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