43 lines
1.1 KiB
Tcl
43 lines
1.1 KiB
Tcl
# Comprehensive VerilogReader coverage test
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# Exercises: assign, bus ports, concatenation, hierarchical modules,
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# ordered port connections, write verilog roundtrip
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source ../../test/helpers.tcl
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puts "--- Test 1: Read comprehensive verilog ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_coverage_test.v
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link_design verilog_coverage_test
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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puts "PASS: read"
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puts "--- Test 2: Timing ---"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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set_input_transition 0.1 [all_inputs]
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report_checks
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puts "PASS: timing"
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puts "--- Test 3: Write verilog ---"
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set outfile [make_result_file verilog_coverage_out.v]
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write_verilog $outfile
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puts "output size: [file size $outfile]"
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puts "PASS: write"
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puts "--- Test 4: Hierarchical queries ---"
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set hier [get_cells -hierarchical *]
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puts "hierarchical cells: [llength $hier]"
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puts "ALL PASSED"
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