45 lines
1.4 KiB
Plaintext
45 lines
1.4 KiB
Plaintext
--- Test 1: Read comprehensive verilog ---
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cells: 13
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nets: 40
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ports: 22
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PASS: read
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--- Test 2: Timing ---
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Warning: verilog_coverage.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
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Startpoint: data_in[0] (input port clocked by clk)
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Endpoint: valid (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_in[0] (in)
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0.06 0.06 v b0/Z (BUF_X1)
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0.02 0.08 v lo_proc/b0/Z (BUF_X1)
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0.02 0.11 v and_const/ZN (AND2_X1)
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0.04 0.14 v or_valid/ZN (OR2_X1)
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0.00 0.14 v valid (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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9.86 slack (MET)
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PASS: timing
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--- Test 3: Write verilog ---
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output size: 1608
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PASS: write
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--- Test 4: Hierarchical queries ---
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hierarchical cells: 21
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ALL PASSED
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