293 lines
7.5 KiB
Plaintext
293 lines
7.5 KiB
Plaintext
--- Test 1: read verilog with constants ---
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cells: 8
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nets: 14
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ports: 8
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and_const: ref=AND2_X1
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or_const: ref=OR2_X1
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buf1: ref=BUF_X1
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inv1: ref=INV_X1
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reg1: ref=DFF_X1
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reg2: ref=DFF_X1
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reg3: ref=DFF_X1
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reg4: ref=DFF_X1
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PASS: read verilog with constants
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--- Test 2: timing with constants ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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2.85 2.85 v or_const/ZN (OR2_X1)
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0.00 2.85 v reg2/D (DFF_X1)
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2.85 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.14 9.86 library setup time
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9.86 data required time
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---------------------------------------------------------
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9.86 data required time
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-2.85 data arrival time
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---------------------------------------------------------
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7.01 slack (MET)
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PASS: report_checks
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg4 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in2 (in)
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-0.98 -0.98 v inv1/ZN (INV_X1)
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0.00 -0.98 v reg4/D (DFF_X1)
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-0.98 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg4/CK (DFF_X1)
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1.14 1.14 library hold time
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1.14 data required time
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---------------------------------------------------------
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1.14 data required time
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0.98 data arrival time
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---------------------------------------------------------
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-2.12 slack (VIOLATED)
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PASS: report_checks min
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No paths found.
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PASS: in1->out1 (and with constant)
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No paths found.
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PASS: in2->out2 (or with constant)
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Warning: verilog_const_concat.tcl line 1, unknown field nets.
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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2 2.34 10.00 0.00 0.00 v in2 (in)
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10.00 0.00 0.00 v or_const/A1 (OR2_X1)
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1 1.06 0.33 2.85 2.85 v or_const/ZN (OR2_X1)
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0.33 0.00 2.85 v reg2/D (DFF_X1)
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2.85 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.14 9.86 library setup time
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9.86 data required time
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-----------------------------------------------------------------------------
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9.86 data required time
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-2.85 data arrival time
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-----------------------------------------------------------------------------
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7.01 slack (MET)
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PASS: report with fields
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--- Test 3: write_verilog ---
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PASS: write_verilog
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PASS: write_verilog -include_pwr_gnd
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PASS: output file exists size=652
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PASS: pwr_gnd file exists size=677
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--- Test 4: net reports ---
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Net n1
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and_const/ZN output (AND2_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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report_net n1: done
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Net n2
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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or_const/ZN output (OR2_X1)
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Load pins
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reg2/D input (DFF_X1) 1.06-1.14
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report_net n2: done
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Net n3
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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reg3/D input (DFF_X1) 1.06-1.14
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report_net n3: done
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Net n4
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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inv1/ZN output (INV_X1)
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Load pins
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reg4/D input (DFF_X1) 1.06-1.14
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report_net n4: done
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--- Test 5: instance reports ---
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Instance and_const
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Cell: AND2_X1
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Library: NangateOpenCellLibrary
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Path cells: AND2_X1
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Input pins:
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A1 input in1
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A2 input one_
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Output pins:
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ZN output n1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance or_const
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Cell: OR2_X1
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Library: NangateOpenCellLibrary
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Path cells: OR2_X1
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Input pins:
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A1 input in2
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A2 input zero_
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Output pins:
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ZN output n2
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance buf1
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input in1
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Output pins:
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Z output n3
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance inv1
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Cell: INV_X1
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Library: NangateOpenCellLibrary
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Path cells: INV_X1
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Input pins:
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A input in2
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Output pins:
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ZN output n4
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg1
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n1
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CK input clk
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Output pins:
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Q output out1
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg2
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n2
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CK input clk
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Output pins:
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Q output out2
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg3
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n3
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CK input clk
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Output pins:
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Q output out3
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg4
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n4
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CK input clk
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Output pins:
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Q output out4
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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PASS: report_instance all
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--- Test 6: re-read same verilog ---
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Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
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re-read cells: 8
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re-read nets: 14
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PASS: re-read verilog (module re-definition)
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--- Test 7: roundtrip ---
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Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
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roundtrip cells: 8
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roundtrip nets: 14
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PASS: roundtrip
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ALL PASSED
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