323 lines
8.8 KiB
Plaintext
323 lines
8.8 KiB
Plaintext
--- Test 1: read complex bus verilog ---
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cells: 28
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nets: 45
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ports: 27
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PASS: read complex bus verilog
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--- Test 2: bus port queries ---
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data_a* ports: 8
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data_b* ports: 8
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result* ports: 8
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data_a[0]: input
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data_a[1]: input
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data_a[2]: input
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data_a[3]: input
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data_a[4]: input
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data_a[5]: input
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data_a[6]: input
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data_a[7]: input
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result[0]: output
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result[1]: output
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result[2]: output
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result[3]: output
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result[4]: output
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result[5]: output
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result[6]: output
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result[7]: output
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carry direction: output
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overflow direction: output
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--- Test 3: bus wire queries ---
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stage1* nets: 8
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stage2* nets: 8
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stage1[0]: stage1[0]
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stage2[0]: stage2[0]
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stage1[1]: stage1[1]
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stage2[1]: stage2[1]
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stage1[7]: stage1[7]
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stage2[7]: stage2[7]
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stage1[*] nets: 8
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stage2[*] nets: 8
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--- Test 4: bus pin queries ---
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buf_a0 pins: 2
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buf_a0/A dir=input
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buf_a0/Z dir=output
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and0 pins: 3
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and0/A1 dir=input
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and0/A2 dir=input
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and0/ZN dir=output
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reg0 pins: 6
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reg0/IQ dir=internal
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reg0/IQN dir=internal
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reg0/D dir=input
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reg0/CK dir=input
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reg0/Q dir=output
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reg0/QN dir=output
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*/A pins: 10
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*/Z pins: 10
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*/ZN pins: 10
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*/D pins: 8
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*/Q pins: 8
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*/CK pins: 8
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--- Test 5: write verilog with buses ---
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PASS: write_verilog
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PASS: output file exists
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output size: 2075
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PASS: write_verilog -include_pwr_gnd
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PASS: pwr_gnd file exists
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--- Test 6: timing analysis ---
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Startpoint: data_b[7] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_b[7] (in)
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2.19 2.19 v and7/ZN (AND2_X1)
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0.14 2.33 v or_carry/ZN (OR2_X1)
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0.03 2.36 v buf_carry/Z (BUF_X1)
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0.00 2.36 v carry (out)
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2.36 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-2.36 data arrival time
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---------------------------------------------------------
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7.64 slack (MET)
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PASS: report_checks
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Startpoint: data_a[0] (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ data_a[0] (in)
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-0.18 -0.18 ^ buf_a0/Z (BUF_X1)
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0.06 -0.12 ^ and0/ZN (AND2_X1)
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0.00 -0.12 ^ reg0/D (DFF_X1)
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-0.12 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg0/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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0.12 data arrival time
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---------------------------------------------------------
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-0.13 slack (VIOLATED)
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PASS: report_checks min
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No paths found.
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PASS: data_a[0]->result[0]
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No paths found.
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PASS: data_a[7]->result[7]
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Startpoint: data_b[7] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_b[7] (in)
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2.19 2.19 v and7/ZN (AND2_X1)
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0.14 2.33 v or_carry/ZN (OR2_X1)
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0.03 2.36 v buf_carry/Z (BUF_X1)
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0.00 2.36 v carry (out)
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2.36 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-2.36 data arrival time
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---------------------------------------------------------
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7.64 slack (MET)
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PASS: ->carry
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Startpoint: data_b[6] (input port clocked by clk)
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Endpoint: overflow (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_b[6] (in)
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2.19 2.19 v and6/ZN (AND2_X1)
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0.11 2.30 v and_ovfl/ZN (AND2_X1)
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0.03 2.33 v buf_ovfl/Z (BUF_X1)
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0.00 2.33 v overflow (out)
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2.33 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-2.33 data arrival time
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---------------------------------------------------------
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7.67 slack (MET)
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PASS: ->overflow
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Warning: verilog_complex_bus.tcl line 1, unknown field nets.
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Startpoint: data_b[7] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 0.89 10.00 0.00 0.00 v data_b[7] (in)
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10.00 0.00 0.00 v and7/A2 (AND2_X1)
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3 2.73 0.31 2.19 2.19 v and7/ZN (AND2_X1)
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0.31 0.00 2.19 v or_carry/A1 (OR2_X1)
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1 0.88 0.02 0.14 2.33 v or_carry/ZN (OR2_X1)
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0.02 0.00 2.33 v buf_carry/A (BUF_X1)
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1 0.00 0.00 0.03 2.36 v buf_carry/Z (BUF_X1)
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0.00 0.00 2.36 v carry (out)
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2.36 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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-----------------------------------------------------------------------------
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10.00 data required time
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-2.36 data arrival time
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-----------------------------------------------------------------------------
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7.64 slack (MET)
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PASS: report with fields
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--- Test 7: report_net on bus ---
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Net stage1[0]
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf_a0/Z output (BUF_X1)
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Load pins
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and0/A1 input (AND2_X1) 0.87-0.92
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report_net stage1[0]: done
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Net stage1[7]
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf_a7/Z output (BUF_X1)
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Load pins
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and7/A1 input (AND2_X1) 0.87-0.92
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report_net stage1[7]: done
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Net stage2[0]
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and0/ZN output (AND2_X1)
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Load pins
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reg0/D input (DFF_X1) 1.06-1.14
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report_net stage2[0]: done
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Net stage2[7]
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Pin capacitance: 2.73-3.01
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Wire capacitance: 0.00
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Total capacitance: 2.73-3.01
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Number of drivers: 1
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Number of loads: 3
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Number of pins: 4
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Driver pins
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and7/ZN output (AND2_X1)
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Load pins
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and_ovfl/A1 input (AND2_X1) 0.87-0.92
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or_carry/A1 input (OR2_X1) 0.79-0.95
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reg7/D input (DFF_X1) 1.06-1.14
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report_net stage2[7]: done
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Net internal_carry
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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or_carry/ZN output (OR2_X1)
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Load pins
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buf_carry/A input (BUF_X1) 0.88-0.97
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report_net internal_carry: done
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Net internal_overflow
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and_ovfl/ZN output (AND2_X1)
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Load pins
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buf_ovfl/A input (BUF_X1) 0.88-0.97
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report_net internal_overflow: done
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--- Test 8: fanin/fanout ---
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fanin to result[0]: 3
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fanout from data_a[0]: 6
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fanin cells to carry: 7
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ALL PASSED
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