182 lines
5.9 KiB
Tcl
182 lines
5.9 KiB
Tcl
# Test VerilogReader and VerilogWriter with bus part-select, bit-select,
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# concatenation expressions, hierarchical sub-modules with bus ports,
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# and write_verilog roundtrip of bus designs.
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# Targets: VerilogReader.cc uncovered:
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# net_part_select_count_ (part-select parsing, line ~209)
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# net_bit_select_count_ (bit-select, line ~207)
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# net_port_ref_bit_count_ / net_port_ref_part_count_ (port ref bus)
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# concat_count_ (concatenation expression, line ~214)
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# makeCellPorts bus port handling
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# makeModule with port_dcls (bus declarations)
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# linkNetwork with hierarchical bus connections
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# Also targets: VerilogWriter.cc:
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# writeInstBusPin / writeInstBusPinBit (bus port writing)
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# writeWireDcls (bus wire declaration, parseBusName)
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# findHierChildren (hierarchical child discovery)
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# writeModule for hierarchical modules
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 1: Read verilog with bus expressions
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#---------------------------------------------------------------
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puts "--- Test 1: read bus partselect verilog ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_bus_partselect.v
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link_design verilog_bus_partselect
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Verify hierarchical instances
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set hier_cells [get_cells -hierarchical *]
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puts "hierarchical cells: [llength $hier_cells]"
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puts "PASS: read bus partselect verilog"
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#---------------------------------------------------------------
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# Test 2: Timing analysis with bus design
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#---------------------------------------------------------------
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puts "--- Test 2: timing ---"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports data_in*]
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set_input_delay -clock clk 0 [get_ports sel]
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set_output_delay -clock clk 0 [get_ports data_out*]
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set_output_delay -clock clk 0 [get_ports valid]
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set_input_transition 0.1 [all_inputs]
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report_checks
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puts "PASS: report_checks"
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report_checks -path_delay min
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puts "PASS: min path"
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report_checks -from [get_ports {data_in[0]}] -to [get_ports {data_out[0]}]
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puts "PASS: data_in[0]->data_out[0]"
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report_checks -from [get_ports {data_in[4]}] -to [get_ports {data_out[4]}]
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puts "PASS: data_in[4]->data_out[4]"
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report_checks -from [get_ports sel] -to [get_ports valid]
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puts "PASS: sel->valid"
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report_checks -fields {slew cap input_pins nets fanout}
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puts "PASS: report with fields"
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#---------------------------------------------------------------
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# Test 3: Write verilog with bus nets (exercises bus wire dcls)
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#---------------------------------------------------------------
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puts "--- Test 3: write verilog ---"
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set out1 [make_result_file verilog_bus_ps_basic.v]
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write_verilog $out1
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set sz1 [file size $out1]
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puts "basic write: $sz1 bytes"
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puts "PASS: basic write"
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# With power/ground
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set out2 [make_result_file verilog_bus_ps_pwr.v]
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write_verilog -include_pwr_gnd $out2
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set sz2 [file size $out2]
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puts "pwr_gnd write: $sz2 bytes"
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if { $sz2 >= $sz1 } {
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puts "PASS: pwr_gnd >= basic"
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}
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# With remove_cells (empty)
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set out3 [make_result_file verilog_bus_ps_remove.v]
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write_verilog -remove_cells {} $out3
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set sz3 [file size $out3]
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puts "remove_cells write: $sz3 bytes"
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puts "PASS: remove_cells write"
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#---------------------------------------------------------------
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# Test 4: Read back written verilog (roundtrip)
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# Exercises: VerilogReader re-parsing bus declarations from writer output
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#---------------------------------------------------------------
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puts "--- Test 4: roundtrip ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out1
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link_design verilog_bus_partselect
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set cells2 [get_cells *]
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puts "roundtrip cells: [llength $cells2]"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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set_input_transition 0.1 [all_inputs]
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report_checks
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puts "PASS: roundtrip timing"
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# Write again to see if sizes match
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set out4 [make_result_file verilog_bus_ps_roundtrip2.v]
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write_verilog $out4
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set sz4 [file size $out4]
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puts "roundtrip2 write: $sz4 bytes"
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puts "PASS: roundtrip write"
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#---------------------------------------------------------------
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# Test 5: Instance and net reports for bus design
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#---------------------------------------------------------------
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puts "--- Test 5: reports ---"
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# Report bus nets
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foreach net_name {buf_out[0] buf_out[1] buf_out[7] inv_out[0] inv_out[7] mux_out[0] mux_out[7]} {
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catch {report_net $net_name} msg
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puts "report_net $net_name: done"
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}
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# Report instances in hierarchy
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foreach inst_name {buf0 buf7 inv0 inv3 reg0 reg7 or01 mux_lo0} {
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catch {report_instance $inst_name} msg
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puts "report_instance $inst_name: done"
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}
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puts "PASS: instance/net reports"
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#---------------------------------------------------------------
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# Test 6: Hierarchical queries
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#---------------------------------------------------------------
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puts "--- Test 6: hierarchical queries ---"
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# Query through hierarchical path
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catch {report_checks -through [get_pins buf0/Z]} msg
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puts "through buf0/Z: done"
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catch {report_checks -through [get_pins inv0/ZN]} msg
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puts "through inv0/ZN: done"
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catch {report_checks -through [get_pins mux_lo0/ZN]} msg
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puts "through mux_lo0/ZN: done"
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puts "PASS: hierarchical queries"
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#---------------------------------------------------------------
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# Test 7: Network modification in bus design
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#---------------------------------------------------------------
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puts "--- Test 7: modify bus design ---"
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# Add an extra buffer on a bus bit
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set nn [make_net "extra_bus_wire"]
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set ni [make_instance "extra_buf_bus" NangateOpenCellLibrary/BUF_X2]
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connect_pin extra_bus_wire extra_buf_bus/A
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set out5 [make_result_file verilog_bus_ps_modified.v]
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write_verilog $out5
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set sz5 [file size $out5]
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puts "modified write: $sz5 bytes"
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disconnect_pin extra_bus_wire extra_buf_bus/A
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delete_instance extra_buf_bus
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delete_net extra_bus_wire
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puts "PASS: bus design modification"
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puts "ALL PASSED"
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