478 lines
13 KiB
Plaintext
478 lines
13 KiB
Plaintext
--- Test 1: read bus partselect verilog ---
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cells: 38
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nets: 54
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ports: 19
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hierarchical cells: 46
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PASS: read bus partselect verilog
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--- Test 2: timing ---
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Startpoint: data_in[4] (input port clocked by clk)
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Endpoint: reg4 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_in[4] (in)
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0.06 0.06 v buf4/Z (BUF_X1)
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0.02 0.08 v pbuf4/Z (BUF_X1)
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0.02 0.10 v sub_hi/b0/Z (BUF_X1)
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0.02 0.13 v mux_hi0/ZN (AND2_X1)
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0.00 0.13 v reg4/D (DFF_X1)
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0.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg4/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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9.83 slack (MET)
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PASS: report_checks
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Startpoint: sel (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ sel (in)
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0.04 0.04 ^ mux_lo0/ZN (AND2_X1)
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0.00 0.04 ^ reg0/D (DFF_X1)
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0.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg0/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.04 data arrival time
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---------------------------------------------------------
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0.04 slack (MET)
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PASS: min path
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No paths found.
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PASS: data_in[0]->data_out[0]
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No paths found.
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PASS: data_in[4]->data_out[4]
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No paths found.
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PASS: sel->valid
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Warning: verilog_bus_partselect.tcl line 1, unknown field nets.
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Startpoint: data_in[4] (input port clocked by clk)
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Endpoint: reg4 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 0.88 0.10 0.00 0.00 v data_in[4] (in)
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0.10 0.00 0.00 v buf4/A (BUF_X1)
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1 0.88 0.01 0.06 0.06 v buf4/Z (BUF_X1)
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0.01 0.00 0.06 v pbuf4/A (BUF_X1)
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1 0.88 0.00 0.02 0.08 v pbuf4/Z (BUF_X1)
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0.00 0.00 0.08 v sub_hi/b0/A (BUF_X1)
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1 0.87 0.00 0.02 0.10 v sub_hi/b0/Z (BUF_X1)
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0.00 0.00 0.10 v mux_hi0/A1 (AND2_X1)
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1 1.06 0.01 0.02 0.13 v mux_hi0/ZN (AND2_X1)
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0.01 0.00 0.13 v reg4/D (DFF_X1)
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0.13 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg4/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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-----------------------------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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-----------------------------------------------------------------------------
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9.83 slack (MET)
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PASS: report with fields
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--- Test 3: write verilog ---
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basic write: 3096 bytes
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PASS: basic write
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pwr_gnd write: 3096 bytes
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PASS: pwr_gnd >= basic
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remove_cells write: 3096 bytes
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PASS: remove_cells write
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--- Test 4: roundtrip ---
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Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
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roundtrip cells: 38
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Warning: verilog_bus_partselect.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
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Startpoint: data_in[4] (input port clocked by clk)
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Endpoint: reg4 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_in[4] (in)
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0.06 0.06 v buf4/Z (BUF_X1)
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0.02 0.08 v pbuf4/Z (BUF_X1)
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0.02 0.10 v sub_hi/b0/Z (BUF_X1)
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0.02 0.13 v mux_hi0/ZN (AND2_X1)
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0.00 0.13 v reg4/D (DFF_X1)
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0.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg4/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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9.83 slack (MET)
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PASS: roundtrip timing
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roundtrip2 write: 3096 bytes
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PASS: roundtrip write
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--- Test 5: reports ---
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Net buf_out[0]
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Pin capacitance: 1.55-1.70
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Wire capacitance: 0.00
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Total capacitance: 1.55-1.70
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf0/Z output (BUF_X1)
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Load pins
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inv0/A input (INV_X1) 1.55-1.70
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report_net buf_out[0]: done
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Net buf_out[1]
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Pin capacitance: 1.55-1.70
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Wire capacitance: 0.00
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Total capacitance: 1.55-1.70
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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inv1/A input (INV_X1) 1.55-1.70
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report_net buf_out[1]: done
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Net buf_out[7]
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf7/Z output (BUF_X1)
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Load pins
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pbuf7/A input (BUF_X1) 0.88-0.97
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report_net buf_out[7]: done
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Net inv_out[0]
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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inv0/ZN output (INV_X1)
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Load pins
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sub_lo/b0/A input (BUF_X1) 0.88-0.97
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Hierarchical pins
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sub_lo/din[0] input
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report_net inv_out[0]: done
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Net inv_out[7]
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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pbuf7/Z output (BUF_X1)
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Load pins
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sub_hi/b3/A input (BUF_X1) 0.88-0.97
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Hierarchical pins
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sub_hi/din[3] input
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report_net inv_out[7]: done
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Net mux_out[0]
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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mux_lo0/ZN output (AND2_X1)
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Load pins
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reg0/D input (DFF_X1) 1.06-1.14
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report_net mux_out[0]: done
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Net mux_out[7]
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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mux_hi3/ZN output (AND2_X1)
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Load pins
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reg7/D input (DFF_X1) 1.06-1.14
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report_net mux_out[7]: done
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Instance buf0
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input data_in[0]
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Output pins:
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Z output buf_out[0]
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance buf0: done
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Instance buf7
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input data_in[7]
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Output pins:
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Z output buf_out[7]
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance buf7: done
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Instance inv0
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Cell: INV_X1
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Library: NangateOpenCellLibrary
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Path cells: INV_X1
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Input pins:
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A input buf_out[0]
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Output pins:
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ZN output inv_out[0]
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance inv0: done
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Instance inv3
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Cell: INV_X1
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Library: NangateOpenCellLibrary
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Path cells: INV_X1
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Input pins:
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A input buf_out[3]
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Output pins:
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ZN output inv_out[3]
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance inv3: done
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Instance reg0
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input mux_out[0]
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CK input clk
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Output pins:
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Q output data_out[0]
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance reg0: done
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Instance reg7
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input mux_out[7]
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CK input clk
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Output pins:
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Q output data_out[7]
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance reg7: done
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Instance or01
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Cell: OR2_X1
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Library: NangateOpenCellLibrary
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Path cells: OR2_X1
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Input pins:
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A1 input data_out[0]
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A2 input data_out[1]
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Output pins:
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ZN output n2
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance or01: done
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Instance mux_lo0
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Cell: AND2_X1
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Library: NangateOpenCellLibrary
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Path cells: AND2_X1
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Input pins:
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A1 input low_nibble[0]
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A2 input sel
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Output pins:
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ZN output mux_out[0]
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance mux_lo0: done
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PASS: instance/net reports
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--- Test 6: hierarchical queries ---
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Startpoint: data_in[0] (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_in[0] (in)
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0.06 0.06 v buf0/Z (BUF_X1)
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0.01 0.07 ^ inv0/ZN (INV_X1)
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0.02 0.09 ^ sub_lo/b0/Z (BUF_X1)
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0.03 0.11 ^ mux_lo0/ZN (AND2_X1)
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0.00 0.11 ^ reg0/D (DFF_X1)
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0.11 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg0/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.11 data arrival time
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---------------------------------------------------------
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9.85 slack (MET)
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through buf0/Z: done
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Startpoint: data_in[0] (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_in[0] (in)
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0.06 0.06 v buf0/Z (BUF_X1)
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0.01 0.07 ^ inv0/ZN (INV_X1)
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0.02 0.09 ^ sub_lo/b0/Z (BUF_X1)
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0.03 0.11 ^ mux_lo0/ZN (AND2_X1)
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0.00 0.11 ^ reg0/D (DFF_X1)
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0.11 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg0/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.11 data arrival time
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---------------------------------------------------------
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9.85 slack (MET)
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through inv0/ZN: done
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Startpoint: data_in[0] (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_in[0] (in)
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0.06 0.06 v buf0/Z (BUF_X1)
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0.01 0.07 ^ inv0/ZN (INV_X1)
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0.02 0.09 ^ sub_lo/b0/Z (BUF_X1)
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0.03 0.11 ^ mux_lo0/ZN (AND2_X1)
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0.00 0.11 ^ reg0/D (DFF_X1)
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0.11 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg0/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.11 data arrival time
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---------------------------------------------------------
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9.85 slack (MET)
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through mux_lo0/ZN: done
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PASS: hierarchical queries
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--- Test 7: modify bus design ---
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modified write: 3162 bytes
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PASS: bus design modification
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ALL PASSED
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