21 lines
715 B
Verilog
21 lines
715 B
Verilog
// Verilog design with assign statements and continuous assignments
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// Exercises VerilogReader.cc assign statement paths
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module verilog_assign_test (clk, in1, in2, in3, out1, out2, out3);
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input clk, in1, in2, in3;
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output out1, out2, out3;
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wire n1, n2, n3, n4, n5;
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wire assigned_net;
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// Continuous assignment (assign statement)
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assign assigned_net = in3;
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BUF_X1 buf1 (.A(in1), .Z(n1));
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BUF_X1 buf2 (.A(in2), .Z(n2));
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AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n3));
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INV_X1 inv1 (.A(n3), .ZN(n4));
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OR2_X1 or1 (.A1(n4), .A2(assigned_net), .ZN(n5));
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DFF_X1 reg1 (.D(n3), .CK(clk), .Q(out1));
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DFF_X1 reg2 (.D(n5), .CK(clk), .Q(out2));
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DFF_X1 reg3 (.D(assigned_net), .CK(clk), .Q(out3));
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endmodule
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