154 lines
4.6 KiB
Tcl
154 lines
4.6 KiB
Tcl
# Test verilog with assign statements and continuous assignments
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# Targets: VerilogReader.cc uncovered functions:
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# makeAssign (line 510, hit=0), VerilogAssign constructor (line 1061, hit=0)
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# mergeAssignNet (line 2102, hit=0)
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# makeDclArg with VerilogAssign (line 454, hit=0)
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# makeNetConstant (line 477, hit=0)
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# VerilogDcl constructor (line 963, hit=0)
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# VerilogDclBus constructor (line 1006, 1018, hit=0)
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# Also exercises: VerilogLex.ll (assign keyword lexing)
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# VerilogParse.yy (assign statement parsing)
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# VerilogWriter.cc (writeAssigns, line 439)
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 1: Read verilog with assign statement
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#---------------------------------------------------------------
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puts "--- Test 1: read verilog with assign ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_assign_test.v
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link_design verilog_assign_test
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Verify specific cells exist
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foreach cell_name {buf1 buf2 and1 inv1 or1 reg1 reg2 reg3} {
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catch {
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set inst [get_cells $cell_name]
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set ref [get_property $inst ref_name]
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puts "$cell_name: ref=$ref"
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} msg
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}
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puts "PASS: read verilog with assign"
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#---------------------------------------------------------------
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# Test 2: Set up timing and verify assign net connectivity
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#---------------------------------------------------------------
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puts "--- Test 2: timing with assign nets ---"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports in1]
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set_input_delay -clock clk 0 [get_ports in2]
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set_input_delay -clock clk 0 [get_ports in3]
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set_output_delay -clock clk 0 [get_ports out1]
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set_output_delay -clock clk 0 [get_ports out2]
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set_output_delay -clock clk 0 [get_ports out3]
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set_input_transition 10 {in1 in2 in3 clk}
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report_checks
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puts "PASS: report_checks with assign"
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report_checks -path_delay min
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puts "PASS: report_checks min"
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# Check different paths
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report_checks -from [get_ports in1] -to [get_ports out1]
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puts "PASS: in1->out1"
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report_checks -from [get_ports in3] -to [get_ports out2]
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puts "PASS: in3->out2 (through assign)"
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report_checks -from [get_ports in3] -to [get_ports out3]
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puts "PASS: in3->out3 (through assign)"
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# Report with various fields
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report_checks -fields {slew cap input_pins nets fanout}
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puts "PASS: report with fields"
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#---------------------------------------------------------------
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# Test 3: Query objects related to assign
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#---------------------------------------------------------------
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puts "--- Test 3: assign-related queries ---"
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# Query nets involved in assign
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catch {
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set assigned [get_nets assigned_net]
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puts "assigned_net found: [get_full_name $assigned]"
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} msg
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# Query internal nets
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foreach net_name {n1 n2 n3 n4 n5} {
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catch {
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set net [get_nets $net_name]
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puts "net $net_name: [get_full_name $net]"
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} msg
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}
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# Report nets
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foreach net_name {n1 n3 n5} {
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catch {report_net $net_name} msg
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puts "report_net $net_name: done"
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}
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# Report instances
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foreach inst_name {buf1 and1 inv1 or1 reg1 reg2} {
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report_instance $inst_name
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puts "report_instance $inst_name: done"
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}
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#---------------------------------------------------------------
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# Test 4: Write verilog and verify
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#---------------------------------------------------------------
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puts "--- Test 4: write verilog ---"
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set outfile [make_result_file verilog_assign_out.v]
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write_verilog $outfile
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puts "PASS: write_verilog"
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if { [file exists $outfile] && [file size $outfile] > 0 } {
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puts "PASS: output file exists and non-empty"
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puts "output size: [file size $outfile]"
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}
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# Write with pwr_gnd
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set outfile2 [make_result_file verilog_assign_pwr.v]
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write_verilog -include_pwr_gnd $outfile2
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puts "PASS: write_verilog -include_pwr_gnd"
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if { [file exists $outfile2] && [file size $outfile2] > 0 } {
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puts "PASS: pwr_gnd file exists and non-empty"
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}
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#---------------------------------------------------------------
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# Test 5: Get fanin/fanout through assign
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#---------------------------------------------------------------
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puts "--- Test 5: fanin/fanout through assign ---"
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catch {
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set fi [get_fanin -to [get_ports out2] -flat]
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puts "fanin to out2: [llength $fi]"
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} msg
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catch {
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set fo [get_fanout -from [get_ports in3] -flat]
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puts "fanout from in3: [llength $fo]"
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} msg
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catch {
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set fi_cells [get_fanin -to [get_ports out2] -only_cells]
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puts "fanin cells to out2: [llength $fi_cells]"
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} msg
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catch {
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set fo_cells [get_fanout -from [get_ports in3] -only_cells]
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puts "fanout cells from in3: [llength $fo_cells]"
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} msg
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puts "ALL PASSED"
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