253 lines
6.4 KiB
Plaintext
253 lines
6.4 KiB
Plaintext
--- Test 1: read verilog with assign ---
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cells: 8
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nets: 13
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ports: 7
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buf1: ref=BUF_X1
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buf2: ref=BUF_X1
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and1: ref=AND2_X1
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inv1: ref=INV_X1
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or1: ref=OR2_X1
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reg1: ref=DFF_X1
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reg2: ref=DFF_X1
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reg3: ref=DFF_X1
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PASS: read verilog with assign
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--- Test 2: timing with assign nets ---
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Startpoint: in3 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in3 (in)
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0.00 0.00 v reg3/D (DFF_X1)
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0.00 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-3.03 6.97 library setup time
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6.97 data required time
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---------------------------------------------------------
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6.97 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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6.97 slack (MET)
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PASS: report_checks with assign
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Startpoint: in3 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in3 (in)
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0.00 0.00 v reg3/D (DFF_X1)
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0.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg3/CK (DFF_X1)
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9.01 9.01 library hold time
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9.01 data required time
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---------------------------------------------------------
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9.01 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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-9.01 slack (VIOLATED)
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PASS: report_checks min
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No paths found.
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PASS: in1->out1
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No paths found.
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PASS: in3->out2 (through assign)
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No paths found.
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PASS: in3->out3 (through assign)
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Warning: verilog_assign.tcl line 1, unknown field nets.
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Startpoint: in3 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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2 1.96 10.00 0.00 0.00 v in3 (in)
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10.00 0.00 0.00 v reg3/D (DFF_X1)
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0.00 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-3.03 6.97 library setup time
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6.97 data required time
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-----------------------------------------------------------------------------
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6.97 data required time
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-0.00 data arrival time
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-----------------------------------------------------------------------------
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6.97 slack (MET)
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PASS: report with fields
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--- Test 3: assign-related queries ---
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assigned_net found: in3
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net n1: n1
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net n2: n2
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net n3: n3
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net n4: n4
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net n5: n5
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Net n1
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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and1/A1 input (AND2_X1) 0.87-0.92
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report_net n1: done
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Net n3
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Pin capacitance: 2.61-2.84
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Wire capacitance: 0.00
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Total capacitance: 2.61-2.84
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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inv1/A input (INV_X1) 1.55-1.70
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reg1/D input (DFF_X1) 1.06-1.14
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report_net n3: done
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Net n5
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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or1/ZN output (OR2_X1)
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Load pins
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reg2/D input (DFF_X1) 1.06-1.14
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report_net n5: done
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Instance buf1
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input in1
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Output pins:
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Z output n1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance buf1: done
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Instance and1
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Cell: AND2_X1
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Library: NangateOpenCellLibrary
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Path cells: AND2_X1
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Input pins:
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A1 input n1
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A2 input n2
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Output pins:
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ZN output n3
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance and1: done
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Instance inv1
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Cell: INV_X1
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Library: NangateOpenCellLibrary
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Path cells: INV_X1
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Input pins:
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A input n3
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Output pins:
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ZN output n4
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance inv1: done
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Instance or1
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Cell: OR2_X1
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Library: NangateOpenCellLibrary
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Path cells: OR2_X1
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Input pins:
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A1 input n4
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A2 input in3
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Output pins:
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ZN output n5
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance or1: done
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Instance reg1
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n3
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CK input clk
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Output pins:
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Q output out1
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance reg1: done
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Instance reg2
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n5
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CK input clk
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Output pins:
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Q output out2
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QN output (unconnected)
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Other pins:
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IQ internal (unconnected)
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IQN internal (unconnected)
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VDD power (unconnected)
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VSS ground (unconnected)
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report_instance reg2: done
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--- Test 4: write verilog ---
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PASS: write_verilog
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PASS: output file exists and non-empty
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output size: 606
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PASS: write_verilog -include_pwr_gnd
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PASS: pwr_gnd file exists and non-empty
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--- Test 5: fanin/fanout through assign ---
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fanin to out2: 3
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fanout from in3: 5
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fanin cells to out2: 2
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fanout cells from in3: 4
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ALL PASSED
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