156 lines
5.6 KiB
CMake
156 lines
5.6 KiB
CMake
add_test(
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NAME tcl.verilog.roundtrip
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_roundtrip
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.roundtrip PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.write_options
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_write_options
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.write_options PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.read_asap7
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_read_asap7
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.read_asap7 PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.attributes
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_attributes
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.attributes PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.specify
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_specify
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.specify PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.writer_advanced
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_writer_advanced
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.writer_advanced PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.bus
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_bus
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.bus PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.assign
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_assign
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.assign PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.complex_bus
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_complex_bus
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.complex_bus PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.write_types
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_write_types
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.write_types PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.hier_write
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_hier_write
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.hier_write PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.supply_tristate
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_supply_tristate
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.supply_tristate PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.const_concat
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_const_concat
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.const_concat PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.escaped_write
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_escaped_write
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.escaped_write PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.remove_cells
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_remove_cells
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.remove_cells PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.error_paths
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_error_paths
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.error_paths PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.preproc_param
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_preproc_param
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.preproc_param PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.gcd_writer
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_gcd_writer
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.gcd_writer PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.bus_partselect
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_bus_partselect
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.bus_partselect PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.gcd_large
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_gcd_large
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.gcd_large PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.multimodule_write
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_multimodule_write
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.multimodule_write PROPERTIES LABELS "tcl;module_verilog")
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add_test(
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NAME tcl.verilog.coverage
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> verilog_coverage
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.verilog.coverage PROPERTIES LABELS "tcl;module_verilog")
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add_subdirectory(cpp)
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