--- Test 1: baseline timing --- Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: baseline Startpoint: in4 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ in4 (in) 0.01 0.01 v nor1/ZN (NOR2_X1) 0.00 0.01 v reg2/D (DFF_X1) 0.01 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.01 data arrival time --------------------------------------------------------- 0.01 slack (MET) PASS: baseline min --- Test 2: incremental delay tolerance --- PASS: set tolerance 0.5 No paths found. PASS: after slew change with large tolerance No paths found. PASS: after slew revert with large tolerance PASS: set tolerance 0.001 No paths found. PASS: after slew change with small tolerance No paths found. PASS: after slew revert with small tolerance PASS: set tolerance 0.0 --- Test 3: incremental load changes --- No paths found. load=0.0001: done No paths found. load=0.001: done No paths found. load=0.005: done No paths found. load=0.01: done No paths found. load=0.05: done No paths found. load=0.1: done No paths found. load=0.5: done Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: load on all outputs --- Test 4: incremental slew changes --- Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.02 0.02 v buf3/Z (BUF_X4) 0.02 0.04 v and1/ZN (AND2_X1) 0.05 0.10 v or1/ZN (OR2_X1) 0.02 0.12 ^ nor1/ZN (NOR2_X1) 0.00 0.12 ^ reg2/D (DFF_X1) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -0.12 data arrival time --------------------------------------------------------- 9.85 slack (MET) PASS: very fast slew Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: medium slew Startpoint: in1 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in1 (in) 0.44 0.44 v buf1/Z (BUF_X1) 0.03 0.47 ^ inv1/ZN (INV_X1) 0.02 0.49 ^ buf2/Z (BUF_X2) 0.03 0.52 ^ or1/ZN (OR2_X1) 0.01 0.53 v nor1/ZN (NOR2_X1) 0.00 0.53 v reg2/D (DFF_X1) 0.53 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.12 9.88 library setup time 9.88 data required time --------------------------------------------------------- 9.88 data required time -0.53 data arrival time --------------------------------------------------------- 9.35 slack (MET) PASS: very slow slew Startpoint: in4 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in4 (in) 0.24 0.24 ^ nor1/ZN (NOR2_X1) 0.00 0.24 ^ reg2/D (DFF_X1) 0.24 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.05 9.95 library setup time 9.95 data required time --------------------------------------------------------- 9.95 data required time -0.24 data arrival time --------------------------------------------------------- 9.71 slack (MET) PASS: mixed slews --- Test 5: constraint changes --- Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 5.00 5.00 clock clk (rise edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 clock reconvergence pessimism 5.00 ^ reg2/CK (DFF_X1) -0.04 4.96 library setup time 4.96 data required time --------------------------------------------------------- 4.96 data required time -0.15 data arrival time --------------------------------------------------------- 4.81 slack (MET) PASS: clock period 5 Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 20.00 20.00 clock clk (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism 20.00 ^ reg2/CK (DFF_X1) -0.04 19.96 library setup time 19.96 data required time --------------------------------------------------------- 19.96 data required time -0.15 data arrival time --------------------------------------------------------- 19.81 slack (MET) PASS: clock period 20 No paths found. PASS: input_delay 2.0 Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) PASS: output_delay 3.0 --- Test 6: network modification invalidation --- PASS: make_instance PASS: make_net PASS: connect_pin Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: report after add PASS: disconnect_pin PASS: cleanup Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: report after cleanup --- Test 7: replace cell --- No paths found. PASS: replace buf1 -> BUF_X4 No paths found. PASS: replace buf1 -> BUF_X2 No paths found. PASS: replace buf1 -> BUF_X1 (restore) Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.02 0.08 v and1/ZN (AND2_X2) 0.05 0.12 v or1/ZN (OR2_X2) 0.02 0.14 ^ nor1/ZN (NOR2_X1) 0.00 0.14 ^ reg2/D (DFF_X1) 0.14 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.14 data arrival time --------------------------------------------------------- 9.82 slack (MET) PASS: replace multiple cells Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: restore cells --- Test 8: tolerance with calculator switching --- Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: lumped_cap with tolerance Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: dmp_ceff_elmore with tolerance Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: dmp_ceff_two_pole with tolerance Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ in1 (in) 1.00 1.00 ^ buf1/Z (BUF_X1) 1.00 2.00 v inv1/ZN (INV_X1) 1.00 3.00 v buf2/Z (BUF_X2) 1.00 4.00 v or1/ZN (OR2_X1) 1.00 5.00 ^ nand1/ZN (NAND2_X1) 0.00 5.00 ^ reg1/D (DFF_X1) 5.00 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFF_X1) -1.00 9.00 library setup time 9.00 data required time --------------------------------------------------------- 9.00 data required time -5.00 data arrival time --------------------------------------------------------- 4.00 slack (MET) PASS: unit with tolerance Startpoint: in2 (input port clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v in2 (in) 0.05 0.05 v buf3/Z (BUF_X4) 0.03 0.08 v and1/ZN (AND2_X1) 0.05 0.13 v or1/ZN (OR2_X1) 0.02 0.15 ^ nor1/ZN (NOR2_X1) 0.00 0.15 ^ reg2/D (DFF_X1) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFF_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -0.15 data arrival time --------------------------------------------------------- 9.81 slack (MET) PASS: final report ALL PASSED