OpenSTA/verilog
Jaehyun Kim d4ad9312ea Merge origin/master into secure-sta-test-suite
Resolve add/add conflict in test/helpers.tcl by merging both versions:
- Keep master's report_file, report_file_filter, sort_objects functions
- Keep branch's diff_files, diff_files_sorted functions
- Use master's result_dir setup with branch's mkdir logic in make_result_file

Resolve content conflict in test/regression by keeping branch's
bash/ctest launcher over master's Tcl regression script.

Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-03-11 09:48:28 +09:00
..
test test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
Verilog.i rel 3.0 2026-01-13 09:36:45 -07:00
Verilog.tcl rel 3.0 2026-01-13 09:36:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy rel 3.0 2026-01-13 09:36:45 -07:00
VerilogReader.cc StdStringSet -> StringSet 2026-03-08 15:55:12 -07:00
VerilogReaderPvt.hh StdStringSet -> StringSet 2026-03-08 15:55:12 -07:00
VerilogScanner.hh LibExpr/spef/saif c++ parsers 2025-02-01 14:49:30 -08:00
VerilogWriter.cc Write verilog escape (#394) 2026-03-02 16:48:15 -08:00