OpenSTA/verilog/test
dsengupta0628 d47cbeb76b fix to exclude bias pins from timing graph
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
2026-04-02 00:56:38 +00:00
..
cpp update test infra to accomodate std::string instead of const char* 2026-03-30 19:44:26 +00:00
CMakeLists.txt fix to exclude bias pins from timing graph 2026-04-02 00:56:38 +00:00
assign_net.v test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
bus_connect.v test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
constant_net.v test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
positional.v test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
regression test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
save_ok test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
verilog_bias_pins.ok fix to exclude bias pins from timing graph 2026-04-02 00:56:38 +00:00
verilog_bias_pins.tcl fix to exclude bias pins from timing graph 2026-04-02 00:56:38 +00:00
verilog_bias_pins.v fix to exclude bias pins from timing graph 2026-04-02 00:56:38 +00:00
verilog_bias_pins_out.vok fix to exclude bias pins from timing graph 2026-04-02 00:56:38 +00:00
verilog_bus.ok test: Fix test failures after master merge 2026-03-11 10:16:27 +09:00
verilog_bus.tcl test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
verilog_bus_out.vok test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00
verilog_bus_test.v test: Add comprehensive test infrastructure and test cases across all OpenSTA modules 2026-02-27 12:59:25 +09:00