82 lines
2.8 KiB
Tcl
82 lines
2.8 KiB
Tcl
# Test 1: Write with -remove_cells option (nangate45 design)
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# Test 4: Read back written file with removed cells
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 1: Write with -remove_cells option (nangate45 design)
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#---------------------------------------------------------------
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puts "--- Test 1: write with -remove_cells ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_test1.v
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link_design verilog_test1
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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# Write without remove
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set out_basic [make_result_file verilog_remove_basic.v]
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write_verilog $out_basic
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# Write with empty remove_cells list
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set out_empty [make_result_file verilog_remove_empty.v]
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write_verilog -remove_cells {} $out_empty
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set sz_basic [file size $out_basic]
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set sz_empty [file size $out_empty]
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puts "basic size=$sz_basic empty remove size=$sz_empty"
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# Write with specific cells to remove (BUF_X1)
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set out_rm_buf [make_result_file verilog_remove_buf.v]
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write_verilog -remove_cells {NangateOpenCellLibrary/BUF_X1} $out_rm_buf
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set sz_rm_buf [file size $out_rm_buf]
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puts "remove BUF_X1 size=$sz_rm_buf"
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# Write with DFF_X1 removed
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set out_rm_dff [make_result_file verilog_remove_dff.v]
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write_verilog -remove_cells {NangateOpenCellLibrary/DFF_X1} $out_rm_dff
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set sz_rm_dff [file size $out_rm_dff]
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puts "remove DFF_X1 size=$sz_rm_dff"
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# Write with both removed
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set out_rm_both [make_result_file verilog_remove_both.v]
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write_verilog -remove_cells {NangateOpenCellLibrary/BUF_X1 NangateOpenCellLibrary/DFF_X1} $out_rm_both
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set sz_rm_both [file size $out_rm_both]
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puts "remove both size=$sz_rm_both"
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# Write with pwr_gnd and remove
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set out_rm_pwr [make_result_file verilog_remove_pwr.v]
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write_verilog -include_pwr_gnd -remove_cells {NangateOpenCellLibrary/BUF_X1} $out_rm_pwr
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set sz_rm_pwr [file size $out_rm_pwr]
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puts "remove+pwr size=$sz_rm_pwr"
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#---------------------------------------------------------------
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# Test 4: Read back written file with removed cells
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# Exercises: link_design with make_black_boxes when cells missing
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#---------------------------------------------------------------
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puts "--- Test 4: read back removed cells ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out_rm_buf
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link_design verilog_test1
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set rt_cells [get_cells *]
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puts "roundtrip (buf removed) cells: [llength $rt_cells]"
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# Read back with all libs (should link normally)
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out_basic
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link_design verilog_test1
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set rt2_cells [get_cells *]
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puts "roundtrip basic cells: [llength $rt2_cells]"
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# Timing on roundtrip
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports in1]
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set_output_delay -clock clk 0 [get_ports out1]
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set_input_transition 0.1 [all_inputs]
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report_checks
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