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OpenSTA/liberty
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JayPankajPatel 88fa9bb0a4 Fix bit_width calculation for ascending bus ranges in writeBusDcls 
std::abs(from - to + 1) gives the wrong result when from < to
(ascending ranges, e.g. [0:10]): abs(0 - 10 + 1) = 9 instead of 11.

Moving +1 outside abs fixes both ascending and descending ranges:
  ascending  [0:10]:  abs(0  - 10) + 1 = 11 (correct)
  descending [10:0]:  abs(10 - 0)  + 1 = 11 (correct)

Fixes #360
 		2026-05-11 01:50:01 -07:00
..
test update tests golden outputs and one cpp file to accomodate new changes in upstream OSTA. functionality remains the same 2026-04-20 15:05:37 +00:00
EquivCells.cc tidy round1 2026-04-13 14:59:05 -07:00
FuncExpr.cc tidy round1 2026-04-13 14:59:05 -07:00
InternalPower.cc tidy round1 2026-04-13 14:59:05 -07:00
LeakagePower.cc tidy round1 2026-04-13 14:59:05 -07:00
LibExprLex.ll tidy round1 2026-04-13 14:59:05 -07:00
LibExprParse.yy string squash 2026-03-28 19:13:35 -07:00
LibExprReader.cc tidy round1 2026-04-13 14:59:05 -07:00
LibExprReader.hh tidy round1 2026-04-13 14:59:05 -07:00
LibExprReaderPvt.hh tidy round1 2026-04-13 14:59:05 -07:00
LibExprScanner.hh tidy round1 2026-04-13 14:59:05 -07:00
Liberty.cc pickup changes from upstream, latest on 4/27 2026-04-27 18:45:35 +00:00
Liberty.i rm extra swig module dcls 2026-04-16 15:46:32 -07:00
Liberty.tcl update copyright 2026-03-10 14:57:45 -07:00
LibertyBuilder.cc tidy round1 2026-04-13 14:59:05 -07:00
LibertyBuilder.hh tidy round1 2026-04-13 14:59:05 -07:00
LibertyLex.ll tidy round1 2026-04-13 14:59:05 -07:00
LibertyParse.yy string squash 2026-03-28 19:13:35 -07:00
LibertyParser.cc tidy round1 2026-04-13 14:59:05 -07:00
LibertyParser.hh tidy round1 2026-04-13 14:59:05 -07:00
LibertyReader.cc tidy round1 2026-04-13 14:59:05 -07:00
LibertyReader.hh tidy round1 2026-04-13 14:59:05 -07:00
LibertyReaderPvt.hh tidy round1 2026-04-13 14:59:05 -07:00
LibertyScanner.hh tidy round1 2026-04-13 14:59:05 -07:00
LibertyWriter.cc Fix bit_width calculation for ascending bus ranges in writeBusDcls 2026-05-11 01:50:01 -07:00
LinearModel.cc tidy round1 2026-04-13 14:59:05 -07:00
Sequential.cc tidy round1 2026-04-13 14:59:05 -07:00
TableModel.cc tidy round1 2026-04-13 14:59:05 -07:00
TimingArc.cc LibertyPort::less 2026-04-18 11:39:03 -07:00
TimingModel.cc tidy round1 2026-04-13 14:59:05 -07:00
TimingRole.cc tidy round1 2026-04-13 14:59:05 -07:00
Units.cc tidy round1 2026-04-13 14:59:05 -07:00
Wireload.cc tidy round1 2026-04-13 14:59:05 -07:00