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Fix bit_width calculation for ascending bus ranges in writeBusDcls 

std::abs(from - to + 1) gives the wrong result when from < to
(ascending ranges, e.g. [0:10]): abs(0 - 10 + 1) = 9 instead of 11.

Moving +1 outside abs fixes both ascending and descending ranges:
  ascending  [0:10]:  abs(0  - 10) + 1 = 11 (correct)
  descending [10:0]:  abs(10 - 0)  + 1 = 11 (correct)

Fixes #360
This commit is contained in:
JayPankajPatel 2026-05-11 01:50:01 -07:00
parent 19a2f3a447
commit 88fa9bb0a4
1 changed files with 1 additions and 1 deletions
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2
liberty/LibertyWriter.cc
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@ -275,7 +275,7 @@ LibertyWriter::writeBusDcls()
sta::print(stream_, " type (\"{}\") {{\n", dcl->name());
sta::print(stream_, " base_type : array;\n");
sta::print(stream_, " data_type : bit;\n");
sta::print(stream_, " bit_width : {};\n", std::abs(dcl->from() - dcl->to() + 1));
sta::print(stream_, " bit_width : {};\n", std::abs(dcl->from() - dcl->to()) + 1);
sta::print(stream_, " bit_from : {};\n", dcl->from());
sta::print(stream_, " bit_to : {};\n", dcl->to());
sta::print(stream_, " }}\n");