146 lines
5.2 KiB
Tcl
146 lines
5.2 KiB
Tcl
# Test VerilogReader error handling paths, bus expressions with partial bits,
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# assign statements with concatenation, hierarchical modules, and write options.
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# Targets:
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# VerilogReader.cc: bus expression parsing (bit select, part select),
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# assign statement with concatenation, module not found errors,
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# port mismatch handling, supply nets, multi-module designs,
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# linkNetwork hierarchy paths, mergeAssignNet,
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# makeNetBitSelect, makeNetPartSelect, makeNetConcat,
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# makeAssign, VerilogAssign constructor paths,
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# VerilogDclBus constructor, wire assign in declaration
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# VerilogWriter.cc: writeAssigns, writeChildren, writeWireDcls,
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# writePortDcls with bus ports
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 1: Read hierarchical design with buses and assigns
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#---------------------------------------------------------------
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puts "--- Test 1: read hierarchical bus design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_error_paths.v
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link_design verilog_error_paths
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Verify hierarchical cells
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set hier_cells [get_cells -hierarchical *]
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puts "hierarchical cells: [llength $hier_cells]"
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# Verify bus ports
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set bus_in [get_ports bus_in*]
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puts "bus_in ports: [llength $bus_in]"
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set bus_out [get_ports bus_out*]
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puts "bus_out ports: [llength $bus_out]"
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set din [get_ports din*]
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puts "din ports: [llength $din]"
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set dout [get_ports dout*]
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puts "dout ports: [llength $dout]"
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# Verify sub-module instances
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set sub1 [get_cells sub1]
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set sub1_ref [get_property $sub1 ref_name]
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puts "sub1: ref=$sub1_ref"
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set sub2 [get_cells sub2]
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set sub2_ref [get_property $sub2 ref_name]
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puts "sub2: ref=$sub2_ref"
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#---------------------------------------------------------------
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# Test 2: Timing analysis with bus ports and hierarchical design
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#---------------------------------------------------------------
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puts "--- Test 2: timing analysis ---"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {din[0] din[1] din[2] din[3] sel en}]
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set_input_delay -clock clk 0 [get_ports {bus_in[0] bus_in[1] bus_in[2] bus_in[3] bus_in[4] bus_in[5] bus_in[6] bus_in[7]}]
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set_output_delay -clock clk 0 [get_ports {dout[0] dout[1] dout[2] dout[3] flag}]
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set_output_delay -clock clk 0 [get_ports {bus_out[0] bus_out[1] bus_out[2] bus_out[3] bus_out[4] bus_out[5] bus_out[6] bus_out[7]}]
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set_input_transition 0.1 [all_inputs]
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report_checks
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report_checks -path_delay min
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# Paths through assign statements
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report_checks -from [get_ports sel] -to [get_ports flag]
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# Paths through hierarchical sub-modules
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report_checks -from [get_ports {din[1]}] -to [get_ports {bus_out[0]}]
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report_checks -from [get_ports {din[2]}] -to [get_ports {bus_out[1]}]
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# All path combinations
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foreach from_idx {0 1 2 3} {
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report_checks -from [get_ports "din\[$from_idx\]"] -to [get_ports "dout\[$from_idx\]"]
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puts "din\[$from_idx\]->dout\[$from_idx\]: done"
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}
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report_checks -fields {slew cap input_pins nets fanout}
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#---------------------------------------------------------------
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# Test 3: Fanin/fanout through hierarchy and assigns
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#---------------------------------------------------------------
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puts "--- Test 3: fanin/fanout ---"
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set fi [get_fanin -to [get_ports flag] -flat]
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puts "fanin to flag: [llength $fi]"
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set fo [get_fanout -from [get_ports sel] -flat]
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puts "fanout from sel: [llength $fo]"
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set fi_cells [get_fanin -to [get_ports {dout[0]}] -only_cells]
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puts "fanin cells to dout[0]: [llength $fi_cells]"
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set fo_cells [get_fanout -from [get_ports {din[0]}] -only_cells]
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puts "fanout cells from din[0]: [llength $fo_cells]"
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set fo_end [get_fanout -from [get_ports {din[1]}] -endpoints_only]
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puts "fanout endpoints from din[1]: [llength $fo_end]"
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#---------------------------------------------------------------
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# Test 4: Write verilog with various options
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#---------------------------------------------------------------
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puts "--- Test 4: write verilog ---"
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set out1 [make_result_file verilog_error_paths_out.v]
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write_verilog $out1
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set out2 [make_result_file verilog_error_paths_pwr.v]
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write_verilog -include_pwr_gnd $out2
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#---------------------------------------------------------------
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# Test 5: Report net for bus and assign-related nets
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#---------------------------------------------------------------
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puts "--- Test 5: net reports ---"
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foreach net_name {w1 w2 w3} {
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report_net $net_name
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puts "report_net $net_name: done"
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}
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#---------------------------------------------------------------
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# Test 6: Report instances
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#---------------------------------------------------------------
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puts "--- Test 6: instance reports ---"
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foreach inst_name {buf0 buf1 buf2 buf3 and_en or_sel sub1 sub2 reg0 reg1 reg2 reg3} {
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report_instance $inst_name
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}
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#---------------------------------------------------------------
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# Test 7: Re-read to exercise module re-definition
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#---------------------------------------------------------------
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puts "--- Test 7: re-read ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_error_paths.v
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link_design verilog_error_paths
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puts "re-read cells: [llength [get_cells *]]"
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puts "re-read nets: [llength [get_nets *]]"
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