OpenSTA/spice
Jaehyun Kim 812d26f14c test: Apply review feedback - part4
Remove unnecessary catch blocks in network, parasitics, sdc, spice,
and util test modules. Add report_checks after set_wire_load_model
in parasitics_wireload.tcl to verify timing changes per wireload.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-20 14:13:55 +09:00
..
test test: Apply review feedback - part4 2026-02-20 14:13:55 +09:00
WritePathSpice.cc rm using std::string from headers 2025-05-22 09:25:56 -07:00
WritePathSpice.hh update copyright 2025-01-21 18:54:33 -07:00
WriteSpice.cc WriteSpice rm dead code 2026-01-11 19:52:55 -08:00
WriteSpice.hh Verilog make pins for liberty pg_pins resolves #326 2025-11-07 11:55:43 -07:00
WriteSpice.i class Path replaces PathVertex etc 2025-03-26 18:21:03 -07:00
WriteSpice.tcl update copyright 2025-01-21 18:54:33 -07:00
Xyce.cc update copyright 2025-01-21 18:54:33 -07:00
Xyce.hh update copyright 2025-01-21 18:54:33 -07:00