150 lines
3.8 KiB
Plaintext
150 lines
3.8 KiB
Plaintext
--- cell pattern matching ---
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INV_* matches: 6
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BUF_* matches: 6
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DFF* matches: 8
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NAND* matches: 9
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NOR* matches: 9
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AOI* matches: 15
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OAI* matches: 16
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all cells: 134
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regexp INV_X#: 6
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regexp BUF_X#: 6
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regexp DFF(R|S|RS)_X(1|2): 8
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nocase nand*: 0
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nocase buf_*: 0
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sky inv* matches: 30
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sky buf* matches: 46
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sky dfxtp* matches: 10
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sky sdf* matches: 19
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sky dlx* matches: 7
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sky dlclkp* matches: 6
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sky lsbuf* matches: 7
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sky all cells: 428
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--- port pattern matching ---
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DFF_X1 all ports: 8
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DFF_X1 Q* ports: 2
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DFFR_X1 all ports: 9
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DFFRS_X1 all ports: 10
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DFFRS_X1 S* ports: 1
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DFFRS_X1 R* ports: 1
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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--- instance pattern matching ---
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all cells: 3
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buf* cells: 1
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reg* cells: 1
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and* cells: 1
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Warning: network_cell_match_merge.tcl line 1, instance 'inv*' not found.
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inv* cells: 0
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Warning: network_cell_match_merge.tcl line 1, instance 'or*' not found.
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or* cells: 0
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Warning: network_cell_match_merge.tcl line 1, instance 'n*' not found.
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n* cells: 0
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--- net pattern matching ---
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all nets: 6
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n* nets: 2
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--- net merge operations ---
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merge_net_1 exists, merge_net_2 exists
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merge_buf_a -> BUF_X2: ref=BUF_X2
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merge_buf_b -> BUF_X4: ref=BUF_X4
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merge_buf_b -> INV_X1: ref=BUF_X4
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--- multi-cell connection patterns ---
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Net chain_net_1
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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chain_buf_0/Z output (BUF_X1)
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Load pins
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chain_buf_1/A input (BUF_X1) 0.88-0.97
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Net chain_net_2
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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chain_buf_1/Z output (BUF_X1)
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Load pins
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chain_buf_2/A input (BUF_X1) 0.88-0.97
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Net chain_net_3
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Pin capacitance: 0.88-0.97
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Wire capacitance: 0.00
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Total capacitance: 0.88-0.97
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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chain_buf_2/Z output (BUF_X1)
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Load pins
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chain_buf_3/A input (BUF_X1) 0.88-0.97
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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