OpenSTA/network
Jaehyun Kim 7173c10cc1 test: strengthen assertions, add sorted SDC diff, and clean up tests
- Split oversized test files to stay under 5,000 lines per file:
  TestSdc.cc → TestSdcClasses.cc, TestSdcStaInit.cc, TestSdcStaDesign.cc
  TestSearchStaDesign.cc → TestSearchStaDesign.cc, TestSearchStaDesignB.cc
  TestLibertyStaBasics.cc → TestLibertyStaBasics.cc, TestLibertyStaBasicsB.cc
  TestNetwork.cc → TestNetwork.cc, TestNetworkB.cc
- Replace ~200+ (void) casts with proper EXPECT_* assertions across all
  C++ test files (dcalc, liberty, network, sdc, search, power, spice, util)
- Remove ~55 SUCCEED() and EXPECT_TRUE(true) no-op assertions
- Fix 6 load-only Tcl tests by adding diff_files verification with
  22 new .sdcok golden reference files
- Delete 7 orphan .ok files with no matching .tcl tests
- Add how_to_write_good_tests.md and TODO6.md documenting test quality rules

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-23 17:36:45 +09:00
..
test test: strengthen assertions, add sorted SDC diff, and clean up tests 2026-02-23 17:36:45 +09:00
ConcreteLibrary.cc liberty bundle ports apply func's to members resolves #256 2025-06-16 16:45:21 +02:00
ConcreteNetwork.cc replace_cell w/spef memory issue 2025-12-02 14:29:55 -08:00
HpinDrvrLoad.cc update copyright 2025-01-21 18:54:33 -07:00
Link.tcl update copyright 2025-01-21 18:54:33 -07:00
Network.cc set_min/max_delay -from reg/D startpoint warning resolves #265 2025-07-03 17:08:44 -07:00
Network.i Verilog make pins for liberty pg_pins resolves #326 2025-11-07 11:55:43 -07:00
Network.tcl liberty bundle ports apply func's to members resolves #256 2025-06-16 16:45:21 +02:00
NetworkCmp.cc update copyright 2025-01-21 18:54:33 -07:00
NetworkEdit.i update copyright 2025-01-21 18:54:33 -07:00
NetworkEdit.tcl update copyright 2025-01-21 18:54:33 -07:00
ParseBus.cc update copyright 2025-01-21 18:54:33 -07:00
PortDirection.cc update copyright 2025-01-21 18:54:33 -07:00
SdcNetwork.cc spef support net missing divider escape resolves #311 2025-10-14 15:58:48 -07:00
VerilogNamespace.cc remove using std from headers 2025-04-11 16:59:48 -07:00