Files
OpenSTA/verilog/test/verilog_remove_basic.vok
T
Jaehyun KimandClaude Opus 4.6 b6d598a119 test: strengthen assertions, add sorted SDC diff, and clean up tests
- Add diff_files_sorted to test/helpers.tcl for hash-order-independent
  SDC comparison (fixes non-deterministic write_sdc output ordering)
- Use diff_files_sorted in sdc_derate_disable_deep and
  sdc_port_delay_advanced tests
- Remove stale coverage percentages from test comments (Comment 1)
- Remove unnecessary catch blocks in search property tests (Comment 3)
- Strengthen load-only tests with actual data verification (Comment 8)
- Remove orphan .ok files for deleted monolithic tests (Comment 9)
- Add golden .sdcok/.libok/.vok/.sdfok files for SDC/liberty/verilog
  write-and-diff tests
- Add -B (clean rebuild) option to make_coverage_report.sh
- Replace (void) casts and EXPECT_TRUE(true) with real assertions in
  TestSdc.cc and TestVerilog.cc

Co-Authored-By: Claude Opus 4.6 <[email protected]>
Signed-off-by: Jaehyun Kim <[email protected]>
2026-02-23 11:50:23 +09:00

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module verilog_test1 (clk,
in1,
out1);
input clk;
input in1;
output out1;
wire n1;
BUF_X1 buf1 (.A(in1),
.Z(n1));
DFF_X1 reg1 (.D(n1),
.CK(clk),
.Q(out1));
endmodule