mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-09-01 18:36:42 +02:00
Jaehyun KimandClaude Opus 4.6
b6d598a119
- Add diff_files_sorted to test/helpers.tcl for hash-order-independent SDC comparison (fixes non-deterministic write_sdc output ordering) - Use diff_files_sorted in sdc_derate_disable_deep and sdc_port_delay_advanced tests - Remove stale coverage percentages from test comments (Comment 1) - Remove unnecessary catch blocks in search property tests (Comment 3) - Strengthen load-only tests with actual data verification (Comment 8) - Remove orphan .ok files for deleted monolithic tests (Comment 9) - Add golden .sdcok/.libok/.vok/.sdfok files for SDC/liberty/verilog write-and-diff tests - Add -B (clean rebuild) option to make_coverage_report.sh - Replace (void) casts and EXPECT_TRUE(true) with real assertions in TestSdc.cc and TestVerilog.cc Co-Authored-By: Claude Opus 4.6 <[email protected]> Signed-off-by: Jaehyun Kim <[email protected]>
48 lines
2.3 KiB
Plaintext
48 lines
2.3 KiB
Plaintext
###############################################################################
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# Created by write_sdc
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###############################################################################
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current_design sdc_test2
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
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set_clock_transition 0.1000 [get_clocks {clk1}]
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set_clock_uncertainty -setup 0.2000 clk1
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set_clock_uncertainty -hold 0.1000 clk1
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set_propagated_clock [get_clocks {clk1}]
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create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
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create_generated_clock -name gen_div2 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
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set_clock_latency 0.3000 [get_clocks {clk2}]
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set_clock_latency -source 0.5000 [get_clocks {clk1}]
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set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
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set_input_delay 1.5000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
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set_input_delay 1.8000 -clock [get_clocks {clk1}] -add_delay [get_ports {in3}]
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set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
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set_output_delay 2.5000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
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set_multicycle_path -setup\
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-from [get_ports {in1}]\
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-to [get_ports {out1}] 2
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set_max_delay\
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-from [get_ports {in2}]\
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-to [get_ports {out1}] 8.0000
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set_false_path\
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-from [get_clocks {clk1}]\
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-to [get_clocks {clk2}]
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###############################################################################
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# Environment
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###############################################################################
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set_operating_conditions typical
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set_load -pin_load 0.0500 [get_ports {out1}]
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set_load -pin_load 0.0400 [get_ports {out2}]
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set_driving_cell -lib_cell BUF_X1 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in1}]
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set_input_transition 0.1500 [get_ports {in1}]
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set_case_analysis 0 [get_ports {in3}]
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set_timing_derate -early 0.9500
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set_timing_derate -late 1.0500
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###############################################################################
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# Design Rules
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###############################################################################
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set_max_transition 0.5000 [current_design]
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set_max_capacitance 0.2000 [current_design]
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set_max_fanout 20.0000 [current_design]
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