Akash Levy 44e7316da1 Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135) ...

* Add {`inst`, `cell`, `src`, `nets`} to `report_checks -format json`

* Smallfix

* Improved nets

* Race condition fix

* Fixes

* Small whitespace fix

* Add no paths corner case stuff

* Adjustments to naming of fields

* Requested fixes

* Reintroduce escapeBackslashes, use stringCopy to prevent stack memory warning

* Fix escapeBackslashes to use preferred style

* No backslash escaping

* Make requested fixes

2025-01-13 19:28:04 -08:00

..

asap7_invbuf.lib.gz

CCS sim delay calc

2024-04-19 17:27:21 -07:00

asap7_seq.lib.gz

prima delay calc

2024-06-30 14:44:31 -07:00

asap7_simple.lib.gz

prima delay calc

2024-06-30 14:44:31 -07:00

asap7_small.lib.gz

test/asap7_small.lib.gz

2024-08-12 20:32:42 -07:00

delay_calc.ok

regression update

2022-12-31 16:36:24 -07:00

get_filter.ok

Update docs and make tests self-descriptive

2024-09-12 11:02:12 -07:00

get_filter.tcl

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

get_is_memory.ok

Make is_memory property more sensitive for cells and libcells by also matching on memory groups (#129)

2024-11-20 15:10:12 -08:00

get_is_memory.tcl

Make is_memory property more sensitive for cells and libcells by also matching on memory groups (#129)

2024-11-20 15:10:12 -08:00

get_is_memory.v

Make is_memory property more sensitive for cells and libcells by also matching on memory groups (#129)

2024-11-20 15:10:12 -08:00

get_lib_pins_of_objects.ok

Add -of_objects key to get_lib_pins (#128)

2024-11-16 14:05:34 -08:00

get_lib_pins_of_objects.tcl

Add -of_objects key to get_lib_pins (#128)

2024-11-16 14:05:34 -08:00

get_noargs.ok

Revisions

2024-09-24 21:20:10 -07:00

get_noargs.tcl

Revisions

2024-09-24 21:20:10 -07:00

get_objrefs.ok

Revisions

2024-09-24 21:20:10 -07:00

get_objrefs.tcl

Revisions

2024-09-24 21:20:10 -07:00

gf180mcu_sram.lib.gz

Make is_memory property more sensitive for cells and libcells by also matching on memory groups (#129)

2024-11-20 15:10:12 -08:00

liberty_arcs_one2one_1.lib

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

liberty_arcs_one2one_1.ok

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

liberty_arcs_one2one_1.tcl

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

liberty_arcs_one2one_1.v

Rename files as requested

2024-08-01 21:14:48 -07:00

liberty_arcs_one2one_2.lib

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

liberty_arcs_one2one_2.ok

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

liberty_arcs_one2one_2.tcl

Follow testing guidelines and specify unateness

2024-09-13 00:57:41 -07:00

liberty_arcs_one2one_2.v

Rename files as requested

2024-08-01 21:14:48 -07:00

liberty_latch3.lib

Fix for non-standard latches (#151)

2024-12-19 15:02:03 -08:00

liberty_latch3.ok

Fix for non-standard latches (#151)

2024-12-19 15:02:03 -08:00

liberty_latch3.tcl

Fix for non-standard latches (#151)

2024-12-19 15:02:03 -08:00

min_max_delays.ok

regression update

2022-12-31 16:36:24 -07:00

multi_corner.ok

regression update

2022-12-31 16:36:24 -07:00

power_vcd.ok

power ok

2024-06-11 21:08:58 -07:00

power.ok

power ok

2024-06-11 21:08:58 -07:00

prima3.ok

prima delay calc

2024-06-30 14:44:31 -07:00

prima3.tcl

prima delay calc

2024-06-30 14:44:31 -07:00

reg1_asap7.spef

prima delay calc

2024-06-30 14:44:31 -07:00

reg1_asap7.v

prima delay calc

2024-06-30 14:44:31 -07:00

regression

update copyright

2024-01-11 16:34:49 -08:00

regression_vars.tcl

Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)

2025-01-13 19:28:04 -08:00

regression.tcl

docker valgrind

2025-01-11 10:04:11 -07:00

report_checks_src_attr.ok

Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)

2025-01-13 19:28:04 -08:00

report_checks_src_attr.tcl

Add src_attr field (#108)

2024-10-15 17:28:52 -07:00

report_json1.ok

Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)

2025-01-13 19:28:04 -08:00

report_json1.tcl

Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)

2025-01-13 19:28:04 -08:00

report_json2.ok

Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)

2025-01-13 19:28:04 -08:00

report_json2.tcl

Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)

2025-01-13 19:28:04 -08:00

save_ok

update copyright

2024-01-11 16:34:49 -08:00

sdf_delays.ok

regression update

2022-12-31 16:36:24 -07:00

spef_parasitics.ok

regression update

2022-12-31 16:36:24 -07:00

valgrind.suppress

regression fast

2019-08-09 18:44:31 -07:00

verilog_attribute.ok

Fix parsing error with >2 attributes

2024-03-27 19:33:58 -07:00

verilog_attribute.tcl

compress example liberty files

2024-10-05 18:12:23 -07:00

verilog_attribute.v

Add {instance, cell, verilog_src, pin, net, hier_pins, capacitance} fields to report_checks -format json for paths (#135)

2025-01-13 19:28:04 -08:00