68 lines
1.9 KiB
Verilog
68 lines
1.9 KiB
Verilog
// Comprehensive Verilog test for VerilogReader coverage
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// Exercises: part-select in port connections, constants, assigns
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// Sub-module with 4-bit bus input and output
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module sub4 (input [3:0] d, output [3:0] q);
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BUF_X1 b0 (.A(d[0]), .Z(q[0]));
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BUF_X1 b1 (.A(d[1]), .Z(q[1]));
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BUF_X1 b2 (.A(d[2]), .Z(q[2]));
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BUF_X1 b3 (.A(d[3]), .Z(q[3]));
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endmodule
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module verilog_coverage_test (
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input clk,
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input [7:0] data_in,
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input [3:0] ctrl,
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output [7:0] data_out,
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output valid
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);
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wire [7:0] w1;
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wire [3:0] lo_result;
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wire [3:0] hi_result;
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wire n1;
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// Buffer data_in to w1
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BUF_X1 b0 (.A(data_in[0]), .Z(w1[0]));
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BUF_X1 b1 (.A(data_in[1]), .Z(w1[1]));
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BUF_X1 b2 (.A(data_in[2]), .Z(w1[2]));
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BUF_X1 b3 (.A(data_in[3]), .Z(w1[3]));
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BUF_X1 b4 (.A(data_in[4]), .Z(w1[4]));
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BUF_X1 b5 (.A(data_in[5]), .Z(w1[5]));
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BUF_X1 b6 (.A(data_in[6]), .Z(w1[6]));
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BUF_X1 b7 (.A(data_in[7]), .Z(w1[7]));
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// Part-select in port connection: triggers makeNetPartSelect
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sub4 lo_proc (
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.d(w1[3:0]),
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.q(lo_result)
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);
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// Concatenation in port connection
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sub4 hi_proc (
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.d({w1[7], w1[6], w1[5], w1[4]}),
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.q(hi_result)
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);
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// Assign statements: triggers VerilogAssign constructor
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assign data_out[0] = lo_result[0];
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assign data_out[1] = lo_result[1];
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assign data_out[2] = lo_result[2];
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assign data_out[3] = lo_result[3];
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assign data_out[4] = hi_result[0];
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assign data_out[5] = hi_result[1];
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assign data_out[6] = hi_result[2];
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assign data_out[7] = hi_result[3];
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// Constants in port connections: triggers makeNetConstant, parseConstant10
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AND2_X1 and_const (.A1(lo_result[0]), .A2(1'b1), .ZN(n1));
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// Decimal constant: triggers parseConstant10
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// Note: 1'd1 is a 1-bit decimal constant
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AND2_X1 and_dec (.A1(lo_result[1]), .A2(1'd1), .ZN(data_out[7]));
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// Valid output
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OR2_X1 or_valid (.A1(n1), .A2(hi_result[0]), .ZN(valid));
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endmodule
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