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OpenSTA/verilog
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Jaehyun Kim 43bca8d224 Merge remote-tracking branch 'opensta/master' into secure-sta-test-by-opus 
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
 		2026-03-21 18:54:37 +09:00
..
test test: Fix post-merge build errors and regolden .ok files 2026-03-11 17:11:08 +09:00
Verilog.i update copyright 2026-03-10 14:57:45 -07:00
Verilog.tcl update copyright 2026-03-10 14:57:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy use std::format squash 2026-03-16 15:01:38 -07:00
VerilogReader.cc use std::format squash 2026-03-16 15:01:38 -07:00
VerilogReaderPvt.hh update copyright 2026-03-10 14:57:45 -07:00
VerilogScanner.hh update copyright 2026-03-10 14:57:45 -07:00
VerilogWriter.cc use std::format squash 2026-03-16 15:01:38 -07:00