144 lines
3.0 KiB
Plaintext
144 lines
3.0 KiB
Plaintext
module verilog_bus_partselect (clk,
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data_in,
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sel,
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data_out,
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valid);
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input clk;
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input [7:0] data_in;
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input sel;
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output [7:0] data_out;
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output valid;
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wire n1;
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wire n2;
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wire n3;
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wire [7:0] buf_out;
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wire [3:0] high_nibble;
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wire [7:0] inv_out;
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wire [3:0] low_nibble;
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wire [7:0] mux_out;
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BUF_X1 buf0 (.A(data_in[0]),
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.Z(buf_out[0]));
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BUF_X1 buf1 (.A(data_in[1]),
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.Z(buf_out[1]));
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BUF_X1 buf2 (.A(data_in[2]),
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.Z(buf_out[2]));
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BUF_X1 buf3 (.A(data_in[3]),
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.Z(buf_out[3]));
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BUF_X1 buf4 (.A(data_in[4]),
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.Z(buf_out[4]));
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BUF_X1 buf5 (.A(data_in[5]),
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.Z(buf_out[5]));
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BUF_X1 buf6 (.A(data_in[6]),
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.Z(buf_out[6]));
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BUF_X1 buf7 (.A(data_in[7]),
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.Z(buf_out[7]));
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INV_X1 inv0 (.A(buf_out[0]),
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.ZN(inv_out[0]));
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INV_X1 inv1 (.A(buf_out[1]),
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.ZN(inv_out[1]));
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INV_X1 inv2 (.A(buf_out[2]),
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.ZN(inv_out[2]));
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INV_X1 inv3 (.A(buf_out[3]),
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.ZN(inv_out[3]));
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AND2_X1 mux_hi0 (.A1(high_nibble[0]),
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.A2(n1),
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.ZN(mux_out[4]));
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AND2_X1 mux_hi1 (.A1(high_nibble[1]),
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.A2(n1),
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.ZN(mux_out[5]));
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AND2_X1 mux_hi2 (.A1(high_nibble[2]),
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.A2(n1),
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.ZN(mux_out[6]));
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AND2_X1 mux_hi3 (.A1(high_nibble[3]),
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.A2(n1),
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.ZN(mux_out[7]));
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AND2_X1 mux_lo0 (.A1(low_nibble[0]),
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.A2(sel),
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.ZN(mux_out[0]));
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AND2_X1 mux_lo1 (.A1(low_nibble[1]),
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.A2(sel),
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.ZN(mux_out[1]));
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AND2_X1 mux_lo2 (.A1(low_nibble[2]),
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.A2(sel),
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.ZN(mux_out[2]));
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AND2_X1 mux_lo3 (.A1(low_nibble[3]),
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.A2(sel),
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.ZN(mux_out[3]));
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OR2_X1 or01 (.A1(data_out[0]),
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.A2(data_out[1]),
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.ZN(n2));
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OR2_X1 or23 (.A1(data_out[2]),
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.A2(data_out[3]),
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.ZN(n3));
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OR2_X1 or_final (.A1(n2),
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.A2(n3),
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.ZN(valid));
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BUF_X1 pbuf4 (.A(buf_out[4]),
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.Z(inv_out[4]));
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BUF_X1 pbuf5 (.A(buf_out[5]),
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.Z(inv_out[5]));
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BUF_X1 pbuf6 (.A(buf_out[6]),
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.Z(inv_out[6]));
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BUF_X1 pbuf7 (.A(buf_out[7]),
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.Z(inv_out[7]));
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DFF_X1 reg0 (.D(mux_out[0]),
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.CK(clk),
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.Q(data_out[0]));
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DFF_X1 reg1 (.D(mux_out[1]),
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.CK(clk),
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.Q(data_out[1]));
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DFF_X1 reg2 (.D(mux_out[2]),
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.CK(clk),
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.Q(data_out[2]));
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DFF_X1 reg3 (.D(mux_out[3]),
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.CK(clk),
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.Q(data_out[3]));
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DFF_X1 reg4 (.D(mux_out[4]),
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.CK(clk),
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.Q(data_out[4]));
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DFF_X1 reg5 (.D(mux_out[5]),
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.CK(clk),
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.Q(data_out[5]));
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DFF_X1 reg6 (.D(mux_out[6]),
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.CK(clk),
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.Q(data_out[6]));
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DFF_X1 reg7 (.D(mux_out[7]),
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.CK(clk),
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.Q(data_out[7]));
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INV_X1 sel_inv (.A(sel),
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.ZN(n1));
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bus_sub sub_hi (.din({inv_out[7],
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inv_out[6],
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inv_out[5],
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inv_out[4]}),
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.dout({high_nibble[3],
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high_nibble[2],
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high_nibble[1],
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high_nibble[0]}));
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bus_sub sub_lo (.din({inv_out[3],
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inv_out[2],
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inv_out[1],
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inv_out[0]}),
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.dout({low_nibble[3],
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low_nibble[2],
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low_nibble[1],
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low_nibble[0]}));
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endmodule
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module bus_sub (din,
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dout);
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input [3:0] din;
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output [3:0] dout;
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BUF_X1 b0 (.A(din[0]),
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.Z(dout[0]));
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BUF_X1 b1 (.A(din[1]),
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.Z(dout[1]));
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BUF_X1 b2 (.A(din[2]),
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.Z(dout[2]));
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BUF_X1 b3 (.A(din[3]),
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.Z(dout[3]));
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endmodule
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