eb0446d4e2
* Fir for write_verilog issue 3826 Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * staToVerilog2 remove escaped_name+=ch Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * updated regression to remove \ from module name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * Using helpers.tcl function to redirect results Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * add std::string and remove trailing space, update regression name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> * update regression to reflect correct output verilog name Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> --------- Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com> |
||
|---|---|---|
| .. | ||
| Verilog.i | ||
| Verilog.tcl | ||
| VerilogLex.ll | ||
| VerilogParse.yy | ||
| VerilogReader.cc | ||
| VerilogReaderPvt.hh | ||
| VerilogScanner.hh | ||
| VerilogWriter.cc | ||