James Cherry 26c76cd075 verilog reader make instances with liberty cell

2020-02-01 10:55:27 -07:00

..

Verilog.i

write_verilog escaped bus port name "input [7:0] \in[0] ;"

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Verilog.tcl

write_verilog -sorted -> -sort

2019-06-17 12:33:37 -07:00

VerilogLex.ll

UseSWIG cmake support for swig

2020-01-25 10:38:03 -07:00

VerilogParse.yy

link_design use verilog library to lookup top

2019-06-26 16:01:58 -07:00

VerilogReader.cc

verilog reader make instances with liberty cell

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VerilogReader.hh

rm redundant StaState args

2019-06-17 08:32:28 -07:00

VerilogReaderPvt.hh

link_design use verilog library to lookup top

2019-06-26 16:01:58 -07:00

VerilogWriter.cc

write_verilog escaped bus port name "input [7:0] \in[0] ;"

2019-07-03 21:18:38 -07:00

VerilogWriter.hh

write_verilog -sorted -> -sort

2019-06-17 12:33:37 -07:00