dsengupta0628 0c96ee9a22 upstream changes plus resolved conflict in ci.yml ... Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>		2026-06-29 15:38:16 +00:00
..
test	Fix report_checks -fields {nets} typo to {net} across test scripts	2026-04-06 14:41:40 +09:00
Verilog.i	rm extra swig module dcls	2026-04-16 15:46:32 -07:00
Verilog.tcl	update copyright	2026-03-10 14:57:45 -07:00
VerilogLex.ll	string squash	2026-03-28 19:13:35 -07:00
VerilogParse.yy	comment	2026-06-04 08:54:28 -07:00
VerilogReader.cc	make_net check for existing	2026-06-24 18:02:47 -07:00
VerilogReaderPvt.hh	clang tidy	2026-04-15 09:38:10 -07:00
VerilogScanner.hh	clang tidy	2026-04-15 09:38:10 -07:00
VerilogWriter.cc	Add native gzip compression support to write_verilog (#448)	2026-06-10 09:12:19 -07:00