113 lines
3.8 KiB
Plaintext
113 lines
3.8 KiB
Plaintext
=== before rebuild: in1 (ref_pin) ===
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Startpoint: in1 (input port clocked by clk)
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Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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100.00 100.00 ^ input external delay
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0.00 100.00 ^ in1 (in)
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0.00 100.00 ^ r1/D (DFFHQx4_ASAP7_75t_R)
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100.00 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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-11.41 488.59 library setup time
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488.59 data required time
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---------------------------------------------------------
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488.59 data required time
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-100.00 data arrival time
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---------------------------------------------------------
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388.59 slack (MET)
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=== before rebuild: in2 (control) ===
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Startpoint: in2 (input port clocked by clk)
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Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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100.00 100.00 ^ input external delay
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0.00 100.00 ^ in2 (in)
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0.00 100.00 ^ r2/D (DFFHQx4_ASAP7_75t_R)
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100.00 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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-13.11 486.89 library setup time
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486.89 data required time
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---------------------------------------------------------
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486.89 data required time
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-100.00 data arrival time
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---------------------------------------------------------
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386.89 slack (MET)
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=== after rebuild: in1 (ref_pin) ===
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Startpoint: in1 (input port clocked by clk)
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Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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100.00 100.00 ^ input external delay
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0.00 100.00 ^ in1 (in)
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0.00 100.00 ^ r1/D (DFFHQx4_ASAP7_75t_R)
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100.00 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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-11.41 488.59 library setup time
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488.59 data required time
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---------------------------------------------------------
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488.59 data required time
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-100.00 data arrival time
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---------------------------------------------------------
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388.59 slack (MET)
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=== after rebuild: in2 (control) ===
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Startpoint: in2 (input port clocked by clk)
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Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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100.00 100.00 ^ input external delay
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0.00 100.00 ^ in2 (in)
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0.00 100.00 ^ r2/D (DFFHQx4_ASAP7_75t_R)
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100.00 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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-13.11 486.89 library setup time
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486.89 data required time
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---------------------------------------------------------
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486.89 data required time
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-100.00 data arrival time
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---------------------------------------------------------
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386.89 slack (MET)
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