=== before rebuild: in1 (ref_pin) ===
Startpoint: in1 (input port clocked by clk)
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
 100.00  100.00 ^ input external delay
   0.00  100.00 ^ in1 (in)
   0.00  100.00 ^ r1/D (DFFHQx4_ASAP7_75t_R)
         100.00   data arrival time

 500.00  500.00   clock clk (rise edge)
   0.00  500.00   clock network delay (ideal)
   0.00  500.00   clock reconvergence pessimism
         500.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
 -11.41  488.59   library setup time
         488.59   data required time
---------------------------------------------------------
         488.59   data required time
        -100.00   data arrival time
---------------------------------------------------------
         388.59   slack (MET)


=== before rebuild: in2 (control) ===
Startpoint: in2 (input port clocked by clk)
Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
 100.00  100.00 ^ input external delay
   0.00  100.00 ^ in2 (in)
   0.00  100.00 ^ r2/D (DFFHQx4_ASAP7_75t_R)
         100.00   data arrival time

 500.00  500.00   clock clk (rise edge)
   0.00  500.00   clock network delay (ideal)
   0.00  500.00   clock reconvergence pessimism
         500.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
 -13.11  486.89   library setup time
         486.89   data required time
---------------------------------------------------------
         486.89   data required time
        -100.00   data arrival time
---------------------------------------------------------
         386.89   slack (MET)


=== after rebuild: in1 (ref_pin) ===
Startpoint: in1 (input port clocked by clk)
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
 100.00  100.00 ^ input external delay
   0.00  100.00 ^ in1 (in)
   0.00  100.00 ^ r1/D (DFFHQx4_ASAP7_75t_R)
         100.00   data arrival time

 500.00  500.00   clock clk (rise edge)
   0.00  500.00   clock network delay (ideal)
   0.00  500.00   clock reconvergence pessimism
         500.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
 -11.41  488.59   library setup time
         488.59   data required time
---------------------------------------------------------
         488.59   data required time
        -100.00   data arrival time
---------------------------------------------------------
         388.59   slack (MET)


=== after rebuild: in2 (control) ===
Startpoint: in2 (input port clocked by clk)
Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
 100.00  100.00 ^ input external delay
   0.00  100.00 ^ in2 (in)
   0.00  100.00 ^ r2/D (DFFHQx4_ASAP7_75t_R)
         100.00   data arrival time

 500.00  500.00   clock clk (rise edge)
   0.00  500.00   clock network delay (ideal)
   0.00  500.00   clock reconvergence pessimism
         500.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
 -13.11  486.89   library setup time
         486.89   data required time
---------------------------------------------------------
         486.89   data required time
        -100.00   data arrival time
---------------------------------------------------------
         386.89   slack (MET)