James Cherry
|
5f23536b17
|
support equiv cells across libraries
|
2019-06-20 21:41:49 -07:00 |
James Cherry
|
49b2c3cea7
|
rm redundant StaState args
|
2019-06-17 08:32:28 -07:00 |
James Cherry
|
154dcf0042
|
rm insert_buffer
|
2019-06-14 16:52:34 -07:00 |
James Cherry
|
9659c43590
|
network/sta replaceCell Cell support
|
2019-06-14 12:05:34 -07:00 |
James Cherry
|
6a194ef6ee
|
LibertyCell::higherDrive(), slowerDrive()
|
2019-05-25 17:08:53 -07:00 |
James Cherry
|
895c4c97c1
|
Sta::insert_buffer
|
2019-05-03 08:07:00 -07:00 |
James Cherry
|
2d519b4740
|
ucsd 20190410 seg fault accessing/setting power_default_signal_toggle_rate
|
2019-04-10 20:36:48 -07:00 |
James Cherry
|
fcfec7ae54
|
2.0.13
|
2019-04-01 09:05:07 -07:00 |
James Cherry
|
e141c83b2e
|
cmakefile
|
2019-03-24 23:04:20 -07:00 |
James Cherry
|
e5c9bc43fd
|
2.0.10
|
2019-03-12 17:25:53 -07:00 |
James Cherry
|
0f2dba7eff
|
sync
|
2019-02-26 08:26:12 -08:00 |
James Cherry
|
d8146af755
|
remove autotools/configure support
|
2019-02-16 12:07:59 -08:00 |
James Cherry
|
3f65204717
|
2.0.6
|
2019-01-26 23:03:01 -08:00 |
James Cherry
|
316742202f
|
sync
|
2019-01-16 15:37:31 -08:00 |
James Cherry
|
3d8d088b89
|
sync
|
2019-01-05 16:09:27 -08:00 |
James Cherry
|
b075ccc783
|
update copyright
|
2019-01-01 12:26:11 -08:00 |
James Cherry
|
e1059eac12
|
find_timing_paths
|
2018-12-20 22:41:54 -08:00 |
James Cherry
|
f49dc75d32
|
sync
|
2018-12-05 14:18:41 -08:00 |
James Cherry
|
ddf897d4e6
|
report_power, pocv support
|
2018-11-26 09:15:52 -08:00 |
James Cherry
|
e9bde796ec
|
2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *)
|
2018-11-09 10:04:16 -08:00 |
James Cherry
|
d0ca009460
|
sync
|
2018-10-23 16:28:41 -07:00 |
James Cherry
|
1154fb89fd
|
and then there was light...
|
2018-09-28 08:54:21 -07:00 |