4 Commits

Author	SHA1	Message	Date
James Cherry	e9bde796ec	2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *)	2018-11-09 10:04:16 -08:00
James Cherry	2af22d9331	2018/10/23 read_verilog mod inst with no ports seg fault	2018-10-23 16:24:22 -07:00
James Cherry	e68203dcf4	^/v for arc display	2018-10-02 16:20:18 -07:00
James Cherry	1154fb89fd	and then there was light...	2018-09-28 08:54:21 -07:00