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24 Commits 3 Branches 1 Tag
b075ccc783aae98ee2fdc4475fe08106fcd15380
Commit Graph
11 Commits
Author SHA1 Message Date
James Cherry b075ccc783 update copyright 2019-01-01 12:26:11 -08:00
James Cherry 9435640d5a write_spice alpha 2019-01-01 12:25:25 -08:00
James Cherry a6e21377e6 2.0.2 2018-12-26 11:03:31 -08:00
James Cherry d29d66c7fb INSTALL 2018-12-15 14:40:22 -08:00
James Cherry 3c0d8c7002 dist 2018-12-15 11:08:24 -08:00
James Cherry f49dc75d32 sync 2018-12-05 14:18:41 -08:00
James Cherry c3b1679bd7 OpenSTA.pdf 2018-11-26 11:42:25 -08:00
James Cherry ddf897d4e6 report_power, pocv support 2018-11-26 09:15:52 -08:00
James Cherry e9bde796ec 2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *) 2018-11-09 10:04:16 -08:00
James Cherry 2af22d9331 2018/10/23 read_verilog mod inst with no ports seg fault 2018-10-23 16:24:22 -07:00
James Cherry 1154fb89fd and then there was light... 2018-09-28 08:54:21 -07:00