James Cherry
|
5a5164276e
|
read_liberty check timing arcs
|
2019-03-19 21:30:19 -07:00 |
|
James Cherry
|
5162905e11
|
2.0.11
|
2019-03-17 15:45:59 -07:00 |
|
James Cherry
|
e5c9bc43fd
|
2.0.10
|
2019-03-12 17:25:53 -07:00 |
|
James Cherry
|
dae85f08e0
|
misspelled "Deescription", gcc warnings
|
2019-03-03 17:50:56 -08:00 |
|
James Cherry
|
0f2dba7eff
|
sync
|
2019-02-26 08:26:12 -08:00 |
|
James Cherry
|
d8146af755
|
remove autotools/configure support
|
2019-02-16 12:07:59 -08:00 |
|
James Cherry
|
3f65204717
|
2.0.6
|
2019-01-26 23:03:01 -08:00 |
|
James Cherry
|
92f4968feb
|
write_path_spice bug fixes
|
2019-01-20 09:44:24 -08:00 |
|
James Cherry
|
316742202f
|
sync
|
2019-01-16 15:37:31 -08:00 |
|
James Cherry
|
3d8d088b89
|
sync
|
2019-01-05 16:09:27 -08:00 |
|
James Cherry
|
b075ccc783
|
update copyright
|
2019-01-01 12:26:11 -08:00 |
|
James Cherry
|
4f381f6669
|
2018/12/24 all_fanout from input port
|
2018-12-24 13:07:10 -08:00 |
|
James Cherry
|
e1059eac12
|
find_timing_paths
|
2018-12-20 22:41:54 -08:00 |
|
James Cherry
|
f49dc75d32
|
sync
|
2018-12-05 14:18:41 -08:00 |
|
James Cherry
|
ddf897d4e6
|
report_power, pocv support
|
2018-11-26 09:15:52 -08:00 |
|
James Cherry
|
e9bde796ec
|
2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *)
|
2018-11-09 10:04:16 -08:00 |
|
James Cherry
|
d0ca009460
|
sync
|
2018-10-23 16:28:41 -07:00 |
|
James Cherry
|
1154fb89fd
|
and then there was light...
|
2018-09-28 08:54:21 -07:00 |