James Cherry
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1c8f1ec9fc
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VerilogWriter using instead of include for LibertyCell
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2020-07-18 09:12:38 -07:00 |
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James Cherry
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a5722ae63c
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write_verilog remove_cells use std::vector
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2020-07-15 11:56:11 -07:00 |
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James Cherry
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4fa9e46235
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write_verilog -remove_cells
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2020-07-15 07:56:34 -07:00 |
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James Cherry
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ec856896c7
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verilog read/write to public includes
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2020-04-05 16:56:38 -07:00 |
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James Cherry
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ee326f165c
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public headers in include/sta
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2020-04-05 14:53:44 -07:00 |
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James Cherry
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804953e317
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mv public headers to include/sta
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2020-04-05 11:35:51 -07:00 |
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James Cherry
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4a017e86eb
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update copyright
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2020-03-06 18:50:37 -08:00 |
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James Cherry
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74e287a7eb
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write_verilog escaped bus port name "input [7:0] \in[0] ;"
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2019-07-03 21:18:38 -07:00 |
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James Cherry
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eea6ab1a29
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write_verilog -sorted -> -sort
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2019-06-17 12:33:37 -07:00 |
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James Cherry
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49b2c3cea7
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rm redundant StaState args
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2019-06-17 08:32:28 -07:00 |
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James Cherry
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3f7e207491
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write_verilog
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2019-06-16 21:08:00 -07:00 |
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James Cherry
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b075ccc783
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update copyright
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2019-01-01 12:26:11 -08:00 |
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James Cherry
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1154fb89fd
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and then there was light...
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2018-09-28 08:54:21 -07:00 |