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write_verilog use inout for power/ground 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2024-04-24 09:34:21 -07:00
parent 22453cc8bf
commit fdca0dff7a
1 changed files with 4 additions and 3 deletions
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7
verilog/VerilogWriter.cc
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@ -214,9 +214,9 @@ VerilogWriter::verilogPortDir(PortDirection *dir)
else if (dir == PortDirection::bidirect()) else if (dir == PortDirection::bidirect())
return "inout"; return "inout";
else if (dir == PortDirection::power()) else if (dir == PortDirection::power())
return "input"; return "inout";
else if (dir == PortDirection::ground()) else if (dir == PortDirection::ground())
return "input"; return "inout";
else if (dir == PortDirection::internal()) else if (dir == PortDirection::internal())
return nullptr; return nullptr;
else { else {
@ -412,7 +412,8 @@ VerilogWriter::writeAssigns(Instance *inst)
Net *net = network_->net(term); Net *net = network_->net(term);
Port *port = network_->port(pin); Port *port = network_->port(pin);
if (port if (port
&& network_->direction(port)->isAnyOutput() && (network_->direction(port)->isAnyOutput()
|| network_->direction(port)->isPowerGround())
&& !stringEqual(network_->name(port), network_->name(net))) { && !stringEqual(network_->name(port), network_->name(net))) {
// Port name is different from net name. // Port name is different from net name.
string port_vname = netVerilogName(network_->name(port), string port_vname = netVerilogName(network_->name(port),