diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc
index e3362da3..799495e5 100644
--- a/verilog/VerilogWriter.cc
+++ b/verilog/VerilogWriter.cc
@@ -214,9 +214,9 @@ VerilogWriter::verilogPortDir(PortDirection *dir)
   else if (dir == PortDirection::bidirect())
     return "inout";
   else if (dir == PortDirection::power())
-    return "input";
+    return "inout";
   else if (dir == PortDirection::ground())
-    return "input";
+    return "inout";
   else if (dir == PortDirection::internal())
     return nullptr;
   else {
@@ -412,7 +412,8 @@ VerilogWriter::writeAssigns(Instance *inst)
     Net *net = network_->net(term);
     Port *port = network_->port(pin);
     if (port
-        && network_->direction(port)->isAnyOutput()
+        && (network_->direction(port)->isAnyOutput()
+            || network_->direction(port)->isPowerGround())
         && !stringEqual(network_->name(port), network_->name(net))) {
       // Port name is different from net name.
       string port_vname = netVerilogName(network_->name(port),