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power activity thru regs caps at 1/clk_period 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2022-11-23 22:17:07 -08:00
parent 305d0dee5c
commit fdba9eb279
2 changed files with 20 additions and 3 deletions
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2
include/sta/PowerClass.hh
View File

@ -38,7 +38,9 @@ public:
float duty,
PwrActivityOrigin origin);
float activity() const { return activity_; }
void setActivity(float activity);
float duty() const { return duty_; }
void setDuty(float duty);
PwrActivityOrigin origin() { return origin_; }
const char *originName() const;
void set(float activity,

21
power/Power.cc
View File

@ -572,10 +572,13 @@ Power::seedRegOutputActivities(const Instance *reg,
const Pin *out_pin = network_->findPin(reg, output);
if (!hasUserActivity(out_pin)) {
PwrActivity activity = evalActivity(seq->data(), reg);
// Register output activity cannnot exceed one transition per clock cycle,
// but latch output can.
if (seq->isRegister()
&& activity.activity() > 1.0)
activity.setActivity(1.0);
if (invert)
activity.set(activity.activity(),
1.0 - activity.duty(),
activity.origin());
activity.setDuty(1.0 - activity.duty());
setSeqActivity(reg, output, activity);
}
}
@ -1190,6 +1193,18 @@ PwrActivity::PwrActivity() :
check();
}
void
PwrActivity::setActivity(float activity)
{
activity_ = activity;
}
void
PwrActivity::setDuty(float duty)
{
duty_ = duty;
}
void
PwrActivity::set(float activity,
float duty,