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Merge https://github.com/parallaxsw/OpenSTA/pull/258 

Anticipating the merge to the upstream and trying to stabilize the OR CI.

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
This commit is contained in:
Matt Liberty 2025-06-15 05:31:12 +00:00
parent ffabd65e39 b64d149ce5
commit fa0cdd6529
6 changed files with 26 additions and 8 deletions
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2
include/sta/Bdd.hh
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@ -34,7 +34,7 @@ struct DdManager;
namespace sta { namespace sta {
typedef std::map<const LibertyPort*, DdNode*> BddPortVarMap; typedef std::map<const LibertyPort*, DdNode*, LibertyPortLess> BddPortVarMap;
typedef std::map<unsigned, const LibertyPort*> BddVarIdxPortMap; typedef std::map<unsigned, const LibertyPort*> BddVarIdxPortMap;
class Bdd : public StaState class Bdd : public StaState

6
include/sta/LibertyClass.hh
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@ -145,6 +145,12 @@ enum class TableAxisVariable {
enum class PathType { clk, data, clk_and_data }; enum class PathType { clk, data, clk_and_data };
const int path_type_count = 2; const int path_type_count = 2;
class LibertyPortLess
{
public:
bool operator()(const LibertyPort *port1, const LibertyPort *port2) const;
};
class LibertyPortNameLess class LibertyPortNameLess
{ {
public: public:

7
liberty/Liberty.cc
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@ -2818,6 +2818,13 @@ sortByName(const LibertyPortSet *set)
return ports; return ports;
} }
bool
LibertyPortLess::operator()(const LibertyPort *port1,
const LibertyPort *port2) const
{
return LibertyPort::less(port1, port2);
}
bool bool
LibertyPortNameLess::operator()(const LibertyPort *port1, LibertyPortNameLess::operator()(const LibertyPort *port1,
const LibertyPort *port2) const const LibertyPort *port2) const

6
liberty/LibertyBuilder.cc
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@ -692,10 +692,10 @@ LibertyBuilder::makeMinPulseWidthArcs(LibertyCell *cell,
from_port = to_port; from_port = to_port;
TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, related_out, TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port, related_out,
role, attrs); role, attrs);
for (auto to_rf : RiseFall::range()) { for (const RiseFall *from_rf : RiseFall::range()) {
TimingModel *model = attrs->model(to_rf); TimingModel *model = attrs->model(from_rf);
if (model) if (model)
makeTimingArc(arc_set, to_rf->opposite(), to_rf, model); makeTimingArc(arc_set, from_rf, from_rf->opposite(), model);
} }
return arc_set; return arc_set;
} }

4
liberty/LibertyReader.cc
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@ -2029,8 +2029,8 @@ LibertyReader::makeMinPulseWidthArcs(LibertyPort *port,
attrs = make_shared<TimingArcAttrs>(); attrs = make_shared<TimingArcAttrs>();
attrs->setTimingType(TimingType::min_pulse_width); attrs->setTimingType(TimingType::min_pulse_width);
} }
// rise/fall_constraint model is on the trailing edge of the pulse. // rise/fall_constraint model is on the leading edge of the pulse.
const RiseFall *model_rf = hi_low->opposite(); const RiseFall *model_rf = hi_low;
TimingModel *check_model = TimingModel *check_model =
makeScalarCheckModel(min_width, ScaleFactorType::min_pulse_width, model_rf); makeScalarCheckModel(min_width, ScaleFactorType::min_pulse_width, model_rf);
attrs->setModel(model_rf, check_model); attrs->setModel(model_rf, check_model);

9
liberty/LibertyWriter.cc
View File

@ -426,8 +426,13 @@ LibertyWriter::writeTimingArcSet(const TimingArcSet *arc_set)
for (const RiseFall *rf : RiseFall::range()) { for (const RiseFall *rf : RiseFall::range()) {
TimingArc *arc = arc_set->arcTo(rf); TimingArc *arc = arc_set->arcTo(rf);
if (arc) if (arc) {
writeTimingModels(arc, rf); // Min pulse width arcs are wrt to the leading edge of the pulse.
const RiseFall *model_rf = (arc_set->role() == TimingRole::width())
? rf->opposite()
: rf;
writeTimingModels(arc, model_rf);
}
} }
fprintf(stream_, " }\n"); fprintf(stream_, " }\n");