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prima thread safety 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2024-08-17 11:39:47 -07:00
parent b51885aa37
commit f54ab5b170
2 changed files with 22 additions and 14 deletions
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3
include/sta/Liberty.hh
View File

@ -16,6 +16,8 @@
#pragma once #pragma once
#include <mutex>
#include "MinMax.hh" #include "MinMax.hh"
#include "RiseFallMinMax.hh" #include "RiseFallMinMax.hh"
#include "ConcreteLibrary.hh" #include "ConcreteLibrary.hh"
@ -628,6 +630,7 @@ protected:
LibertyPgPortMap pg_port_map_; LibertyPgPortMap pg_port_map_;
bool has_internal_ports_; bool has_internal_ports_;
bool have_voltage_waveforms_; bool have_voltage_waveforms_;
std::mutex waveform_lock_;
private: private:
friend class LibertyLibrary; friend class LibertyLibrary;

33
liberty/Liberty.cc
View File

@ -16,6 +16,7 @@
#include "Liberty.hh" #include "Liberty.hh"
#include "Mutex.hh"
#include "EnumNameMap.hh" #include "EnumNameMap.hh"
#include "Report.hh" #include "Report.hh"
#include "Debug.hh" #include "Debug.hh"
@ -1963,24 +1964,28 @@ void
LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps) LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps)
{ {
if (!have_voltage_waveforms_) { if (!have_voltage_waveforms_) {
float vdd = 0.0; // shutup gcc LockGuard lock(waveform_lock_);
bool vdd_exists; // Recheck with lock.
liberty_library_->supplyVoltage("VDD", vdd, vdd_exists); if (!have_voltage_waveforms_) {
if (!vdd_exists || vdd == 0.0) float vdd = 0.0; // shutup gcc
criticalError(1120, "library missing vdd"); bool vdd_exists;
for (TimingArcSet *arc_set : timingArcSets()) { liberty_library_->supplyVoltage("VDD", vdd, vdd_exists);
for (TimingArc *arc : arc_set->arcs()) { if (!vdd_exists || vdd == 0.0)
for (const DcalcAnalysisPt *dcalc_ap : dcalc_aps) { criticalError(1120, "library missing vdd");
GateTableModel *model = arc->gateTableModel(dcalc_ap); for (TimingArcSet *arc_set : timingArcSets()) {
if (model) { for (TimingArc *arc : arc_set->arcs()) {
OutputWaveforms *output_waveforms = model->outputWaveforms(); for (const DcalcAnalysisPt *dcalc_ap : dcalc_aps) {
if (output_waveforms) GateTableModel *model = arc->gateTableModel(dcalc_ap);
output_waveforms->ensureVoltageWaveforms(vdd); if (model) {
OutputWaveforms *output_waveforms = model->outputWaveforms();
if (output_waveforms)
output_waveforms->ensureVoltageWaveforms(vdd);
}
} }
} }
} }
have_voltage_waveforms_ = true;
} }
have_voltage_waveforms_ = true;
} }
} }