From f54ab5b17003b5fe721c88d443156bb209718ac7 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Sat, 17 Aug 2024 11:39:47 -0700 Subject: [PATCH] prima thread safety Signed-off-by: James Cherry --- include/sta/Liberty.hh | 3 +++ liberty/Liberty.cc | 33 +++++++++++++++++++-------------- 2 files changed, 22 insertions(+), 14 deletions(-) diff --git a/include/sta/Liberty.hh b/include/sta/Liberty.hh index a18cceec..4763a8d0 100644 --- a/include/sta/Liberty.hh +++ b/include/sta/Liberty.hh @@ -16,6 +16,8 @@ #pragma once +#include + #include "MinMax.hh" #include "RiseFallMinMax.hh" #include "ConcreteLibrary.hh" @@ -628,6 +630,7 @@ protected: LibertyPgPortMap pg_port_map_; bool has_internal_ports_; bool have_voltage_waveforms_; + std::mutex waveform_lock_; private: friend class LibertyLibrary; diff --git a/liberty/Liberty.cc b/liberty/Liberty.cc index 95a9cb48..ac15e702 100644 --- a/liberty/Liberty.cc +++ b/liberty/Liberty.cc @@ -16,6 +16,7 @@ #include "Liberty.hh" +#include "Mutex.hh" #include "EnumNameMap.hh" #include "Report.hh" #include "Debug.hh" @@ -1963,24 +1964,28 @@ void LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps) { if (!have_voltage_waveforms_) { - float vdd = 0.0; // shutup gcc - bool vdd_exists; - liberty_library_->supplyVoltage("VDD", vdd, vdd_exists); - if (!vdd_exists || vdd == 0.0) - criticalError(1120, "library missing vdd"); - for (TimingArcSet *arc_set : timingArcSets()) { - for (TimingArc *arc : arc_set->arcs()) { - for (const DcalcAnalysisPt *dcalc_ap : dcalc_aps) { - GateTableModel *model = arc->gateTableModel(dcalc_ap); - if (model) { - OutputWaveforms *output_waveforms = model->outputWaveforms(); - if (output_waveforms) - output_waveforms->ensureVoltageWaveforms(vdd); + LockGuard lock(waveform_lock_); + // Recheck with lock. + if (!have_voltage_waveforms_) { + float vdd = 0.0; // shutup gcc + bool vdd_exists; + liberty_library_->supplyVoltage("VDD", vdd, vdd_exists); + if (!vdd_exists || vdd == 0.0) + criticalError(1120, "library missing vdd"); + for (TimingArcSet *arc_set : timingArcSets()) { + for (TimingArc *arc : arc_set->arcs()) { + for (const DcalcAnalysisPt *dcalc_ap : dcalc_aps) { + GateTableModel *model = arc->gateTableModel(dcalc_ap); + if (model) { + OutputWaveforms *output_waveforms = model->outputWaveforms(); + if (output_waveforms) + output_waveforms->ensureVoltageWaveforms(vdd); + } } } } + have_voltage_waveforms_ = true; } - have_voltage_waveforms_ = true; } }