luke
/
OpenSTA
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

rm auto's for compile time

This commit is contained in:
James Cherry 2019-11-11 15:53:29 -07:00
parent cc1bd6b5ab
commit de50cc5d67
2 changed files with 82 additions and 82 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
search/Sta.cc
View File

@ -3092,7 +3092,7 @@ Sta::vertexSlew(Vertex *vertex,
{ {
findDelays(vertex); findDelays(vertex);
Slew mm_slew = min_max->initValue(); Slew mm_slew = min_max->initValue();
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { for (DcalcAnalysisPt *dcalc_ap : corners_->dcalcAnalysisPts()) {
Slew slew = graph_->slew(vertex, rf, dcalc_ap->index()); Slew slew = graph_->slew(vertex, rf, dcalc_ap->index());
if (fuzzyGreater(slew, mm_slew, min_max)) if (fuzzyGreater(slew, mm_slew, min_max))
mm_slew = slew; mm_slew = slew;
@ -3200,7 +3200,7 @@ Sta::maxArrivalCountVertex() const
int int
Sta::vertexArrivalCount(Vertex *vertex) const Sta::vertexArrivalCount(Vertex *vertex) const
{ {
auto tag_group = search_->tagGroup(vertex); TagGroup *tag_group = search_->tagGroup(vertex);
if (tag_group) if (tag_group)
return tag_group->arrivalCount(); return tag_group->arrivalCount();
else else
@ -3718,7 +3718,7 @@ Sta::findCellPort(LibertyCell *cell,
{ {
LibertyCellPortIterator port_iter(cell); LibertyCellPortIterator port_iter(cell);
while (port_iter.hasNext()) { while (port_iter.hasNext()) {
auto port = port_iter.next(); LibertyPort *port = port_iter.next();
if (port->direction() == dir) if (port->direction() == dir)
return port; return port;
} }
@ -4731,7 +4731,7 @@ InstanceMaxSlewGreater::instMaxSlew(const Instance *inst) const
if (network->isDriver(pin)) { if (network->isDriver(pin)) {
Vertex *vertex = graph->pinDrvrVertex(pin); Vertex *vertex = graph->pinDrvrVertex(pin);
for (RiseFall *rf : RiseFall::range()) { for (RiseFall *rf : RiseFall::range()) {
for (auto dcalc_ap : sta_->corners()->dcalcAnalysisPts()) { for (DcalcAnalysisPt *dcalc_ap : sta_->corners()->dcalcAnalysisPts()) {
Slew slew = graph->slew(vertex, rf, dcalc_ap->index()); Slew slew = graph->slew(vertex, rf, dcalc_ap->index());
if (slew > max_slew) if (slew > max_slew)
max_slew = slew; max_slew = slew;

156
search/WritePathSpice.cc
View File

@ -293,8 +293,8 @@ WritePathSpice::WritePathSpice(Path *path,
bool exists; bool exists;
default_library_->supplyVoltage(power_name_, power_voltage_, exists); default_library_->supplyVoltage(power_name_, power_voltage_, exists);
if (!exists) { if (!exists) {
auto dcalc_ap = path_->dcalcAnalysisPt(this); DcalcAnalysisPt *dcalc_ap = path_->dcalcAnalysisPt(this);
auto op_cond = dcalc_ap->operatingConditions(); const OperatingConditions *op_cond = dcalc_ap->operatingConditions();
if (op_cond == nullptr) if (op_cond == nullptr)
op_cond = network_->defaultLibertyLibrary()->defaultOperatingConditions(); op_cond = network_->defaultLibertyLibrary()->defaultOperatingConditions();
power_voltage_ = op_cond->voltage(); power_voltage_ = op_cond->voltage();
@ -333,8 +333,8 @@ WritePathSpice::writeSpice()
void void
WritePathSpice::writeHeader() WritePathSpice::writeHeader()
{ {
auto min_max = path_->minMax(this); const MinMax *min_max = path_->minMax(this);
auto pvt = sdc_->operatingConditions(min_max); Pvt *pvt = sdc_->operatingConditions(min_max);
if (pvt == nullptr) if (pvt == nullptr)
pvt = default_library_->defaultOperatingConditions(); pvt = default_library_->defaultOperatingConditions();
Path *start_path = path_expanded_.startPath(); Path *start_path = path_expanded_.startPath();
@ -343,13 +343,13 @@ WritePathSpice::writeHeader()
start_path->transition(this)->asString(), start_path->transition(this)->asString(),
network_->pathName(path_->pin(this)), network_->pathName(path_->pin(this)),
path_->transition(this)->asString()); path_->transition(this)->asString());
auto temp = pvt->temperature(); float temp = pvt->temperature();
streamPrint(spice_stream_, ".temp %.1f\n", temp); streamPrint(spice_stream_, ".temp %.1f\n", temp);
streamPrint(spice_stream_, ".include \"%s\"\n", model_filename_); streamPrint(spice_stream_, ".include \"%s\"\n", model_filename_);
streamPrint(spice_stream_, ".include \"%s\"\n", subckt_filename_); streamPrint(spice_stream_, ".include \"%s\"\n", subckt_filename_);
auto max_time = maxTime(); float max_time = maxTime();
auto time_step = max_time / 1e+3; float time_step = max_time / 1e+3;
streamPrint(spice_stream_, ".tran %.3g %.3g\n\n", streamPrint(spice_stream_, ".tran %.3g %.3g\n\n",
time_step, max_time); time_step, max_time);
} }
@ -357,23 +357,23 @@ WritePathSpice::writeHeader()
float float
WritePathSpice::maxTime() WritePathSpice::maxTime()
{ {
auto input_stage = stageFirst(); Stage input_stage = stageFirst();
auto input_path = stageDrvrPath(input_stage); PathRef *input_path = stageDrvrPath(input_stage);
auto tr = input_path->transition(this); const RiseFall *rf = input_path->transition(this);
auto next_arc = stageGateArc(input_stage + 1); TimingArc *next_arc = stageGateArc(input_stage + 1);
auto input_slew = findSlew(input_path, tr, next_arc); Slew input_slew = findSlew(input_path, rf, next_arc);
if (input_path->isClock(this)) { if (input_path->isClock(this)) {
auto clk = input_path->clock(this); Clock *clk = input_path->clock(this);
auto period = clk->period(); float period = clk->period();
float first_edge_offset = period / 10; float first_edge_offset = period / 10;
auto max_time = period * clk_cycle_count_ + first_edge_offset; float max_time = period * clk_cycle_count_ + first_edge_offset;
return max_time; return max_time;
} }
else { else {
auto end_slew = findSlew(path_); Slew end_slew = findSlew(path_);
auto max_time = delayAsFloat(input_slew float max_time = delayAsFloat(input_slew
+ path_->arrival(this) + path_->arrival(this)
+ end_slew * 2) * 1.5; + end_slew * 2) * 1.5;
return max_time; return max_time;
} }
} }
@ -386,7 +386,7 @@ WritePathSpice::writeStageInstances()
streamPrint(spice_stream_, "*****************\n\n"); streamPrint(spice_stream_, "*****************\n\n");
for (Stage stage = stageFirst(); stage <= stageLast(); stage++) { for (Stage stage = stageFirst(); stage <= stageLast(); stage++) {
auto stage_name = stageName(stage).c_str(); const char *stage_name = stageName(stage).c_str();
if (stage == stageFirst()) if (stage == stageFirst())
streamPrint(spice_stream_, "x%s %s %s %s\n", streamPrint(spice_stream_, "x%s %s %s %s\n",
stage_name, stage_name,
@ -410,7 +410,7 @@ WritePathSpice::pgPortVoltage(LibertyPgPort *pg_port)
LibertyLibrary *liberty = pg_port->cell()->libertyLibrary(); LibertyLibrary *liberty = pg_port->cell()->libertyLibrary();
float voltage = 0.0; float voltage = 0.0;
bool exists; bool exists;
auto voltage_name = pg_port->voltageName(); const char *voltage_name = pg_port->voltageName();
if (voltage_name) { if (voltage_name) {
liberty->supplyVoltage(voltage_name, voltage, exists); liberty->supplyVoltage(voltage_name, voltage, exists);
if (!exists) { if (!exists) {
@ -439,8 +439,8 @@ WritePathSpice::writeInputSource()
streamPrint(spice_stream_, "* Input source\n"); streamPrint(spice_stream_, "* Input source\n");
streamPrint(spice_stream_, "**************\n\n"); streamPrint(spice_stream_, "**************\n\n");
auto input_stage = stageFirst(); Stage input_stage = stageFirst();
auto input_path = stageDrvrPath(input_stage); PathRef *input_path = stageDrvrPath(input_stage);
if (input_path->isClock(this)) if (input_path->isClock(this))
writeClkWaveform(); writeClkWaveform();
else else
@ -451,16 +451,16 @@ WritePathSpice::writeInputSource()
void void
WritePathSpice::writeInputWaveform() WritePathSpice::writeInputWaveform()
{ {
auto input_stage = stageFirst(); Stage input_stage = stageFirst();
auto input_path = stageDrvrPath(input_stage); PathRef *input_path = stageDrvrPath(input_stage);
auto tr = input_path->transition(this); const RiseFall *rf = input_path->transition(this);
auto next_arc = stageGateArc(input_stage + 1); TimingArc *next_arc = stageGateArc(input_stage + 1);
auto slew0 = findSlew(input_path, tr, next_arc); Slew slew0 = findSlew(input_path, rf, next_arc);
// Arbitrary offset. // Arbitrary offset.
auto time0 = slew0; float time0 = slew0;
int volt_index = 1; int volt_index = 1;
auto drvr_pin = stageDrvrPin(input_stage); const Pin *drvr_pin = stageDrvrPin(input_stage);
writeStepVoltSource(drvr_pin, tr, slew0, time0, volt_index); writeStepVoltSource(drvr_pin, rf, slew0, time0, volt_index);
} }
void void
@ -492,12 +492,12 @@ WritePathSpice::writeStepVoltSource(const Pin *pin,
void void
WritePathSpice::writeClkWaveform() WritePathSpice::writeClkWaveform()
{ {
auto input_stage = stageFirst(); Stage input_stage = stageFirst();
auto input_path = stageDrvrPath(input_stage); PathRef *input_path = stageDrvrPath(input_stage);
auto next_arc = stageGateArc(input_stage + 1); TimingArc *next_arc = stageGateArc(input_stage + 1);
auto clk_edge = input_path->clkEdge(this); ClockEdge *clk_edge = input_path->clkEdge(this);
auto clk = clk_edge->clock(); Clock *clk = clk_edge->clock();
auto period = clk->period(); float period = clk->period();
float time_offset = clkWaveformTImeOffset(clk); float time_offset = clkWaveformTImeOffset(clk);
RiseFall *rf0, *rf1; RiseFall *rf0, *rf1;
float volt0; float volt0;
@ -511,14 +511,14 @@ WritePathSpice::writeClkWaveform()
rf1 = RiseFall::rise(); rf1 = RiseFall::rise();
volt0 = power_voltage_; volt0 = power_voltage_;
} }
auto slew0 = findSlew(input_path, rf0, next_arc); Slew slew0 = findSlew(input_path, rf0, next_arc);
auto slew1 = findSlew(input_path, rf1, next_arc); Slew slew1 = findSlew(input_path, rf1, next_arc);
streamPrint(spice_stream_, "v1 %s 0 pwl(\n", streamPrint(spice_stream_, "v1 %s 0 pwl(\n",
stageDrvrPinName(input_stage)); stageDrvrPinName(input_stage));
streamPrint(spice_stream_, "+%.3e %.3e\n", 0.0, volt0); streamPrint(spice_stream_, "+%.3e %.3e\n", 0.0, volt0);
for (int cycle = 0; cycle < clk_cycle_count_; cycle++) { for (int cycle = 0; cycle < clk_cycle_count_; cycle++) {
auto time0 = time_offset + cycle * period; float time0 = time_offset + cycle * period;
auto time1 = time0 + period / 2.0; float time1 = time0 + period / 2.0;
writeWaveformEdge(rf0, time0, slew0); writeWaveformEdge(rf0, time0, slew0);
writeWaveformEdge(rf1, time1, slew1); writeWaveformEdge(rf1, time1, slew1);
} }
@ -557,7 +557,7 @@ WritePathSpice::findSlew(Vertex *vertex,
TimingArc *next_arc, TimingArc *next_arc,
DcalcAPIndex dcalc_ap_index) DcalcAPIndex dcalc_ap_index)
{ {
auto slew = delayAsFloat(graph_->slew(vertex, rf, dcalc_ap_index)); Slew slew = delayAsFloat(graph_->slew(vertex, rf, dcalc_ap_index));
if (slew == 0.0 && next_arc) if (slew == 0.0 && next_arc)
slew = slewAxisMinValue(next_arc); slew = slewAxisMinValue(next_arc);
if (slew == 0.0) if (slew == 0.0)
@ -610,12 +610,12 @@ WritePathSpice::writeWaveformEdge(const RiseFall *rf,
volt0 = power_voltage_; volt0 = power_voltage_;
volt1 = gnd_voltage_; volt1 = gnd_voltage_;
} }
auto threshold = default_library_->inputThreshold(rf); float threshold = default_library_->inputThreshold(rf);
auto lower = default_library_->slewLowerThreshold(rf); float lower = default_library_->slewLowerThreshold(rf);
auto upper = default_library_->slewUpperThreshold(rf); float upper = default_library_->slewUpperThreshold(rf);
auto dt = slew / (upper - lower); float dt = slew / (upper - lower);
auto time0 = time - dt * threshold; float time0 = time - dt * threshold;
auto time1 = time0 + dt; float time1 = time0 + dt;
streamPrint(spice_stream_, "+%.3e %.3e\n", time0, volt0); streamPrint(spice_stream_, "+%.3e %.3e\n", time0, volt0);
streamPrint(spice_stream_, "+%.3e %.3e\n", time1, volt1); streamPrint(spice_stream_, "+%.3e %.3e\n", time1, volt1);
} }
@ -630,9 +630,9 @@ WritePathSpice::writeMeasureStmts()
streamPrint(spice_stream_, "********************\n\n"); streamPrint(spice_stream_, "********************\n\n");
for (Stage stage = stageFirst(); stage <= stageLast(); stage++) { for (Stage stage = stageFirst(); stage <= stageLast(); stage++) {
auto gate_input_path = stageGateInputPath(stage); PathRef *gate_input_path = stageGateInputPath(stage);
auto drvr_path = stageDrvrPath(stage); PathRef *drvr_path = stageDrvrPath(stage);
auto load_path = stageLoadPath(stage); PathRef *load_path = stageLoadPath(stage);
if (gate_input_path) { if (gate_input_path) {
// gate input -> gate output // gate input -> gate output
writeMeasureSlewStmt(stage, gate_input_path); writeMeasureSlewStmt(stage, gate_input_path);
@ -652,13 +652,13 @@ WritePathSpice::writeMeasureDelayStmt(Stage stage,
Path *from_path, Path *from_path,
Path *to_path) Path *to_path)
{ {
auto from_pin_name = network_->pathName(from_path->pin(this)); const char *from_pin_name = network_->pathName(from_path->pin(this));
auto from_rf = from_path->transition(this); const RiseFall *from_rf = from_path->transition(this);
auto from_threshold = power_voltage_ * default_library_->inputThreshold(from_rf); float from_threshold = power_voltage_ * default_library_->inputThreshold(from_rf);
auto to_pin_name = network_->pathName(to_path->pin(this)); const char *to_pin_name = network_->pathName(to_path->pin(this));
auto to_rf = to_path->transition(this); const RiseFall *to_rf = to_path->transition(this);
auto to_threshold = power_voltage_ * default_library_->inputThreshold(to_rf); float to_threshold = power_voltage_ * default_library_->inputThreshold(to_rf);
streamPrint(spice_stream_, streamPrint(spice_stream_,
".measure tran %s_%s_delay_%s\n", ".measure tran %s_%s_delay_%s\n",
stageName(stage).c_str(), stageName(stage).c_str(),
@ -680,13 +680,13 @@ void
WritePathSpice::writeMeasureSlewStmt(Stage stage, WritePathSpice::writeMeasureSlewStmt(Stage stage,
Path *path) Path *path)
{ {
auto pin_name = network_->pathName(path->pin(this)); const char *pin_name = network_->pathName(path->pin(this));
auto tr = path->transition(this); const RiseFall *rf = path->transition(this);
auto spice_rf = spiceTrans(tr); const char *spice_rf = spiceTrans(rf);
auto lower = power_voltage_ * default_library_->slewLowerThreshold(tr); float lower = power_voltage_ * default_library_->slewLowerThreshold(rf);
auto upper = power_voltage_ * default_library_->slewUpperThreshold(tr); float upper = power_voltage_ * default_library_->slewUpperThreshold(rf);
float threshold1, threshold2; float threshold1, threshold2;
if (tr == RiseFall::rise()) { if (rf == RiseFall::rise()) {
threshold1 = lower; threshold1 = lower;
threshold2 = upper; threshold2 = upper;
} }
@ -740,8 +740,8 @@ WritePathSpice::writeInputStage(Stage stage)
{ {
// Input arc. // Input arc.
// External driver not handled. // External driver not handled.
auto drvr_pin_name = stageDrvrPinName(stage); const char *drvr_pin_name = stageDrvrPinName(stage);
auto load_pin_name = stageLoadPinName(stage); const char *load_pin_name = stageLoadPinName(stage);
streamPrint(spice_stream_, ".subckt %s %s %s\n", streamPrint(spice_stream_, ".subckt %s %s %s\n",
stageName(stage).c_str(), stageName(stage).c_str(),
drvr_pin_name, drvr_pin_name,
@ -754,21 +754,21 @@ WritePathSpice::writeInputStage(Stage stage)
void void
WritePathSpice::writeGateStage(Stage stage) WritePathSpice::writeGateStage(Stage stage)
{ {
auto input_pin = stageGateInputPin(stage); const Pin *input_pin = stageGateInputPin(stage);
auto input_pin_name = stageGateInputPinName(stage); const char *input_pin_name = stageGateInputPinName(stage);
auto drvr_pin = stageDrvrPin(stage); const Pin *drvr_pin = stageDrvrPin(stage);
auto drvr_pin_name = stageDrvrPinName(stage); const char *drvr_pin_name = stageDrvrPinName(stage);
auto load_pin = stageLoadPin(stage); const Pin *load_pin = stageLoadPin(stage);
auto load_pin_name = stageLoadPinName(stage); const char *load_pin_name = stageLoadPinName(stage);
streamPrint(spice_stream_, ".subckt stage%d %s %s %s\n", streamPrint(spice_stream_, ".subckt stage%d %s %s %s\n",
stage, stage,
input_pin_name, input_pin_name,
drvr_pin_name, drvr_pin_name,
load_pin_name); load_pin_name);
// Driver subckt call. // Driver subckt call.
auto inst = stageInstance(stage); Instance *inst = stageInstance(stage);
auto input_port = stageGateInputPort(stage); LibertyPort *input_port = stageGateInputPort(stage);
auto drvr_port = stageDrvrPort(stage); LibertyPort *drvr_port = stageDrvrPort(stage);
streamPrint(spice_stream_, "* Gate %s %s -> %s\n", streamPrint(spice_stream_, "* Gate %s %s -> %s\n",
network_->pathName(inst), network_->pathName(inst),
input_port->name(), input_port->name(),
@ -786,7 +786,7 @@ WritePathSpice::writeGateStage(Stage stage)
port_values.clear(); port_values.clear();
auto pin_iter = network_->connectedPinIterator(drvr_pin); auto pin_iter = network_->connectedPinIterator(drvr_pin);
while (pin_iter->hasNext()) { while (pin_iter->hasNext()) {
auto pin = pin_iter->next(); Pin *pin = pin_iter->next();
if (pin != drvr_pin if (pin != drvr_pin
&& pin != load_pin && pin != load_pin
&& network_->direction(pin)->isAnyInput() && network_->direction(pin)->isAnyInput()
@ -1227,7 +1227,7 @@ WritePathSpice::writeStageParasitics(Stage stage)
sort(devices, ParasiticDeviceLess(parasitics_)); sort(devices, ParasiticDeviceLess(parasitics_));
for (auto device : devices) { for (ParasiticDevice *device : devices) {
float resistance = parasitics_->value(device, parasitic_ap); float resistance = parasitics_->value(device, parasitic_ap);
if (parasitics_->isResistor(device)) { if (parasitics_->isResistor(device)) {
ParasiticNode *node1 = parasitics_->node1(device); ParasiticNode *node1 = parasitics_->node1(device);
@ -1262,7 +1262,7 @@ WritePathSpice::writeStageParasitics(Stage stage)
// Add resistors from drvr to load for missing parasitic connections. // Add resistors from drvr to load for missing parasitic connections.
auto pin_iter = network_->connectedPinIterator(drvr_pin); auto pin_iter = network_->connectedPinIterator(drvr_pin);
while (pin_iter->hasNext()) { while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next(); const Pin *pin = pin_iter->next();
if (pin != drvr_pin if (pin != drvr_pin
&& network_->isLoad(pin) && network_->isLoad(pin)
&& !network_->isHierarchical(pin) && !network_->isHierarchical(pin)
@ -1405,7 +1405,7 @@ WritePathSpice::findPathCellnames(// Return values.
Pin *drvr_pin = stageDrvrPin(stage); Pin *drvr_pin = stageDrvrPin(stage);
auto pin_iter = network_->connectedPinIterator(drvr_pin); auto pin_iter = network_->connectedPinIterator(drvr_pin);
while (pin_iter->hasNext()) { while (pin_iter->hasNext()) {
Pin *pin = pin_iter->next(); const Pin *pin = pin_iter->next();
LibertyPort *port = network_->libertyPort(pin); LibertyPort *port = network_->libertyPort(pin);
if (port) { if (port) {
LibertyCell *cell = port->libertyCell(); LibertyCell *cell = port->libertyCell();