mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-09-02 20:18:26 +02:00
Jaehyun Kim
+1
-1
@@ -155,7 +155,7 @@ Report::printToBufferAppend(const char *fmt,
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va_copy(args_copy, args);
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size_t length = vsnprint(buffer_ + buffer_length_, buffer_size_- buffer_length_,
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fmt, args);
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if (length >= buffer_size_) {
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if (length >= buffer_size_ - buffer_length_) {
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buffer_size_ = buffer_length_ + length * 2;
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char *new_buffer = new char[buffer_size_];
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strncpy(new_buffer, buffer_, buffer_length_);
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@@ -0,0 +1,64 @@
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add_test(
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NAME tcl.util.msg_suppress
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_msg_suppress
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.util.msg_suppress PROPERTIES LABELS "tcl;module_util")
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add_test(
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NAME tcl.util.commands
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_commands
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.util.commands PROPERTIES LABELS "tcl;module_util")
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add_test(
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NAME tcl.util.report_redirect
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_report_redirect
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.util.report_redirect PROPERTIES LABELS "tcl;module_util")
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add_test(
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NAME tcl.util.pattern_string
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_pattern_string
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.util.pattern_string PROPERTIES LABELS "tcl;module_util")
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add_test(
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NAME tcl.util.report_debug
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_report_debug
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.util.report_debug PROPERTIES LABELS "tcl;module_util")
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add_test(
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NAME tcl.util.parallel_misc
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_parallel_misc
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.util.parallel_misc PROPERTIES LABELS "tcl;module_util")
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add_test(
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NAME tcl.util.report_format
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_report_format
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.util.report_format PROPERTIES LABELS "tcl;module_util")
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add_test(
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NAME tcl.util.log_redirect
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_log_redirect
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.util.log_redirect PROPERTIES LABELS "tcl;module_util")
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add_test(
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NAME tcl.util.report_string_log
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COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> util_report_string_log
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WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
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)
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set_tests_properties(tcl.util.report_string_log PROPERTIES LABELS "tcl;module_util")
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add_subdirectory(cpp)
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@@ -0,0 +1,16 @@
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add_executable(TestUtil TestUtil.cc)
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target_link_libraries(TestUtil
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OpenSTA
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GTest::gtest
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GTest::gtest_main
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${TCL_LIBRARY}
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)
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target_include_directories(TestUtil PRIVATE
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${STA_HOME}/include/sta
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${STA_HOME}
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${CMAKE_BINARY_DIR}/include/sta
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)
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gtest_discover_tests(TestUtil
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WORKING_DIRECTORY ${STA_HOME}
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PROPERTIES LABELS "cpp;module_util"
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)
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File diff suppressed because it is too large
Load Diff
Symlink
+1
@@ -0,0 +1 @@
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../../test/regression
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@@ -0,0 +1,54 @@
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--- set_cmd_units -time ns -capacitance pF -resistance kOhm ---
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PASS: set_cmd_units ns/pF/kOhm
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--- report_units ---
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time 1ns
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capacitance 1pF
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resistance 1kohm
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voltage 1v
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current 1A
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power 1W
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distance 1m
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--- set_cmd_units -time ps -capacitance fF ---
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PASS: set_cmd_units ps/fF
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--- report_units after change ---
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time 1ps
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capacitance 1fF
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resistance 1kohm
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voltage 1v
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current 1A
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power 1W
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distance 1m
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--- set_cmd_units -voltage mV ---
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PASS: set_cmd_units -voltage mV
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--- set_cmd_units -current uA ---
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PASS: set_cmd_units -current uA
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--- set_cmd_units -distance um ---
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PASS: set_cmd_units -distance um
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--- report_units after all changes ---
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time 1ps
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capacitance 1fF
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resistance 1kohm
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voltage 1mv
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current 1uA
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power 1W
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distance 1um
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--- elapsed_run_time ---
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PASS: elapsed_run_time returned non-negative value
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--- user_run_time ---
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PASS: user_run_time returned non-negative value
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--- log_begin / log_end ---
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test log entry from util_commands
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PASS: log_begin/log_end completed
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PASS: log file has content
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--- suppress_msg / unsuppress_msg ---
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PASS: suppress_msg 100 200 300
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PASS: unsuppress_msg 100 200 300
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--- suppress_msg single ---
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PASS: suppress_msg 999
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PASS: unsuppress_msg 999
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--- with_output_to_variable ---
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captured output length: 95
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PASS: with_output_to_variable captured output
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--- with_output_to_variable second call ---
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PASS: with_output_to_variable second call
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ALL PASSED
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@@ -0,0 +1,96 @@
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# Test utility commands
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puts "--- set_cmd_units -time ns -capacitance pF -resistance kOhm ---"
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set_cmd_units -time ns -capacitance pF -resistance kOhm
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puts "PASS: set_cmd_units ns/pF/kOhm"
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puts "--- report_units ---"
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report_units
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puts "--- set_cmd_units -time ps -capacitance fF ---"
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set_cmd_units -time ps -capacitance fF
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puts "PASS: set_cmd_units ps/fF"
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puts "--- report_units after change ---"
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report_units
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puts "--- set_cmd_units -voltage mV ---"
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set_cmd_units -voltage mV
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puts "PASS: set_cmd_units -voltage mV"
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puts "--- set_cmd_units -current uA ---"
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set_cmd_units -current uA
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puts "PASS: set_cmd_units -current uA"
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puts "--- set_cmd_units -distance um ---"
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set_cmd_units -distance um
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puts "PASS: set_cmd_units -distance um"
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puts "--- report_units after all changes ---"
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report_units
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puts "--- elapsed_run_time ---"
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set elapsed [elapsed_run_time]
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if { $elapsed >= 0 } {
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puts "PASS: elapsed_run_time returned non-negative value"
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} else {
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puts "FAIL: elapsed_run_time returned negative"
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}
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puts "--- user_run_time ---"
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set user_time [user_run_time]
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if { $user_time >= 0 } {
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puts "PASS: user_run_time returned non-negative value"
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} else {
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puts "FAIL: user_run_time returned negative"
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}
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puts "--- log_begin / log_end ---"
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set log_file "/tmp/sta_test_log_[pid].txt"
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log_begin $log_file
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puts "test log entry from util_commands"
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log_end
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puts "PASS: log_begin/log_end completed"
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# Verify log file was created and has content
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if { [file exists $log_file] } {
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set fh [open $log_file r]
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set log_content [read $fh]
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close $fh
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file delete $log_file
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if { [string length $log_content] > 0 } {
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puts "PASS: log file has content"
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} else {
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puts "INFO: log file was empty"
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}
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} else {
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puts "INFO: log file not found (may be expected)"
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}
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puts "--- suppress_msg / unsuppress_msg ---"
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suppress_msg 100 200 300
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puts "PASS: suppress_msg 100 200 300"
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unsuppress_msg 100 200 300
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puts "PASS: unsuppress_msg 100 200 300"
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puts "--- suppress_msg single ---"
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suppress_msg 999
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puts "PASS: suppress_msg 999"
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unsuppress_msg 999
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puts "PASS: unsuppress_msg 999"
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puts "--- with_output_to_variable ---"
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with_output_to_variable result { report_units }
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puts "captured output length: [string length $result]"
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if { [string length $result] > 0 } {
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puts "PASS: with_output_to_variable captured output"
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} else {
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puts "FAIL: with_output_to_variable captured empty output"
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}
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puts "--- with_output_to_variable second call ---"
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with_output_to_variable result2 { puts "hello from with_output_to_variable" }
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puts "PASS: with_output_to_variable second call"
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puts "ALL PASSED"
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@@ -0,0 +1,180 @@
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--- Test 1: log with timing reports ---
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
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Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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0.04 0.04 ^ r3/Q (DFFHQx4_ASAP7_75t_R)
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||||
0.00 0.04 ^ out (out)
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0.04 data arrival time
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||||
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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-1.00 499.00 output external delay
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499.00 data required time
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---------------------------------------------------------
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499.00 data required time
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-0.04 data arrival time
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---------------------------------------------------------
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498.96 slack (MET)
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||||
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||||
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||||
Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
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||||
Path Type: min
|
||||
|
||||
Delay Time Description
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||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
0.04 0.04 v r1/Q (DFFHQx4_ASAP7_75t_R)
|
||||
0.02 0.06 v u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 0.06 v r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
0.06 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-0.06 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.05 slack (MET)
|
||||
|
||||
|
||||
No paths found.
|
||||
Warning: util_log_redirect.tcl line 1, unknown field nets.
|
||||
Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
1 0.00 0.01 0.04 0.04 ^ r3/Q (DFFHQx4_ASAP7_75t_R)
|
||||
0.00 0.00 0.04 ^ out (out)
|
||||
0.04 data arrival time
|
||||
|
||||
0.00 500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (ideal)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
-1.00 499.00 output external delay
|
||||
499.00 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
499.00 data required time
|
||||
-0.04 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
498.96 slack (MET)
|
||||
|
||||
|
||||
time 1ns
|
||||
capacitance 1fF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
PASS: log with timing reports
|
||||
PASS: log file has 3404 chars
|
||||
--- Test 2: simultaneous log and redirect ---
|
||||
Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
0.04 0.04 v r1/Q (DFFHQx4_ASAP7_75t_R)
|
||||
0.02 0.06 v u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 0.06 v r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
0.06 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-0.06 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.05 slack (MET)
|
||||
|
||||
|
||||
PASS: simultaneous log and redirect
|
||||
PASS: log file has 2022 chars
|
||||
PASS: redirect file has 997 chars
|
||||
--- Test 3: redirect file append ---
|
||||
PASS: redirect file append (3 writes)
|
||||
PASS: appended file has 2022 chars
|
||||
--- Test 4: redirect to string ---
|
||||
captured string 1: 902 chars
|
||||
captured string 2: 1120 chars
|
||||
with_output v1: 902 chars
|
||||
with_output v2: 2022 chars
|
||||
PASS: redirect to string
|
||||
--- Test 5: log + redirect string ---
|
||||
log+string captured: 997 chars
|
||||
PASS: log + redirect string
|
||||
--- Test 6: message suppression ---
|
||||
PASS: caught error
|
||||
PASS: suppress/unsuppress
|
||||
--- Test 7: report formatting ---
|
||||
time 1ps
|
||||
capacitance 1fF
|
||||
resistance 1ohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
time 1us
|
||||
capacitance 1nF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
PASS: report formatting
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,215 @@
|
||||
# Test Report.cc log + redirect interaction, buffer growth, and
|
||||
# simultaneous log+console output.
|
||||
# Targets: Report.cc uncovered functions:
|
||||
# logBegin/logEnd with real report output,
|
||||
# redirectFileAppendBegin with log active,
|
||||
# redirectStringBegin/End with log active,
|
||||
# printString with log_stream_ active (both redirect and log paths),
|
||||
# printLine, printConsole, reportLine, reportLineString,
|
||||
# buffer growth (printToBufferAppend with oversized strings),
|
||||
# warn/fileWarn with suppressed IDs
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Log file with real timing reports
|
||||
# Exercises: logBegin, logEnd, printString with log_stream_ active
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: log with timing reports ---"
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog ../../test/reg1_asap7.v
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
read_verilog ../../test/reg1_asap7.v
|
||||
link_design top
|
||||
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 1 {in1 in2}
|
||||
set_output_delay -clock clk 1 [get_ports out]
|
||||
|
||||
set log_file1 [make_result_file "util_log_timing.log"]
|
||||
log_begin $log_file1
|
||||
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_units
|
||||
|
||||
log_end
|
||||
puts "PASS: log with timing reports"
|
||||
|
||||
# Verify log file has content
|
||||
if { [file exists $log_file1] } {
|
||||
set fh [open $log_file1 r]
|
||||
set content [read $fh]
|
||||
close $fh
|
||||
set len [string length $content]
|
||||
if { $len > 100 } {
|
||||
puts "PASS: log file has $len chars"
|
||||
} else {
|
||||
puts "INFO: log file unexpectedly small: $len"
|
||||
}
|
||||
} else {
|
||||
puts "INFO: log file not found"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Simultaneous log + redirect
|
||||
# Exercises: printString with both log_stream_ and redirect_stream_
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: simultaneous log and redirect ---"
|
||||
|
||||
set log_file2 [make_result_file "util_simultaneous.log"]
|
||||
set redir_file2 [make_result_file "util_simultaneous_redir.txt"]
|
||||
|
||||
log_begin $log_file2
|
||||
|
||||
sta::redirect_file_begin $redir_file2
|
||||
report_checks
|
||||
report_units
|
||||
sta::redirect_file_end
|
||||
|
||||
# Now output goes to console + log only
|
||||
report_checks -path_delay min
|
||||
|
||||
log_end
|
||||
puts "PASS: simultaneous log and redirect"
|
||||
|
||||
# Verify both files have content
|
||||
foreach {fname label} [list $log_file2 "log" $redir_file2 "redirect"] {
|
||||
if { [file exists $fname] } {
|
||||
set fh [open $fname r]
|
||||
set content [read $fh]
|
||||
close $fh
|
||||
set len [string length $content]
|
||||
if { $len > 0 } {
|
||||
puts "PASS: $label file has $len chars"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Redirect file append with multiple writes
|
||||
# Exercises: redirectFileAppendBegin, redirectFileEnd
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: redirect file append ---"
|
||||
|
||||
set append_file [make_result_file "util_append.txt"]
|
||||
|
||||
# First write
|
||||
sta::redirect_file_begin $append_file
|
||||
report_units
|
||||
sta::redirect_file_end
|
||||
|
||||
# Append second write
|
||||
sta::redirect_file_append_begin $append_file
|
||||
report_checks
|
||||
sta::redirect_file_end
|
||||
|
||||
# Append third write
|
||||
sta::redirect_file_append_begin $append_file
|
||||
report_checks -path_delay min
|
||||
sta::redirect_file_end
|
||||
|
||||
puts "PASS: redirect file append (3 writes)"
|
||||
|
||||
if { [file exists $append_file] } {
|
||||
set fh [open $append_file r]
|
||||
set content [read $fh]
|
||||
close $fh
|
||||
set len [string length $content]
|
||||
if { $len > 200 } {
|
||||
puts "PASS: appended file has $len chars"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Redirect to string capturing timing output
|
||||
# Exercises: redirectStringBegin, redirectStringEnd,
|
||||
# redirectStringPrint, printString redirect_to_string_ path
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: redirect to string ---"
|
||||
|
||||
sta::redirect_string_begin
|
||||
report_checks
|
||||
set str1 [sta::redirect_string_end]
|
||||
puts "captured string 1: [string length $str1] chars"
|
||||
|
||||
sta::redirect_string_begin
|
||||
report_checks -path_delay min
|
||||
report_units
|
||||
set str2 [sta::redirect_string_end]
|
||||
puts "captured string 2: [string length $str2] chars"
|
||||
|
||||
# Capture with with_output_to_variable (uses same redirect string path)
|
||||
with_output_to_variable v1 { report_checks }
|
||||
puts "with_output v1: [string length $v1] chars"
|
||||
|
||||
with_output_to_variable v2 { report_checks; report_units; report_checks -path_delay min }
|
||||
puts "with_output v2: [string length $v2] chars"
|
||||
|
||||
puts "PASS: redirect to string"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Log + redirect string simultaneously
|
||||
# Exercises: printString with both log_stream_ and redirect_to_string_
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: log + redirect string ---"
|
||||
|
||||
set log_file3 [make_result_file "util_log_str.log"]
|
||||
log_begin $log_file3
|
||||
|
||||
sta::redirect_string_begin
|
||||
report_checks
|
||||
report_units
|
||||
set str3 [sta::redirect_string_end]
|
||||
|
||||
log_end
|
||||
|
||||
puts "log+string captured: [string length $str3] chars"
|
||||
puts "PASS: log + redirect string"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Message suppression with warnings
|
||||
# Exercises: isSuppressed, warn with suppressed IDs
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: message suppression ---"
|
||||
|
||||
suppress_msg 100 200 300
|
||||
# Trigger some warnings by reading nonexistent files
|
||||
set rc [catch { read_liberty "/nonexistent/path.lib" } msg]
|
||||
if { $rc != 0 } {
|
||||
puts "PASS: caught error"
|
||||
}
|
||||
|
||||
unsuppress_msg 100 200 300
|
||||
puts "PASS: suppress/unsuppress"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Various report formatting
|
||||
# Exercises: reportLine, reportBlankLine, reportLineString
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: report formatting ---"
|
||||
|
||||
set_cmd_units -time ps -capacitance fF -resistance Ohm
|
||||
report_units
|
||||
|
||||
set_cmd_units -time ns -capacitance pF -resistance kOhm -voltage V -current mA -power mW
|
||||
report_units
|
||||
|
||||
set_cmd_units -time us -capacitance nF
|
||||
report_units
|
||||
|
||||
# Reset to defaults
|
||||
set_cmd_units -time ns -capacitance pF -resistance kOhm
|
||||
report_units
|
||||
puts "PASS: report formatting"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,5 @@
|
||||
PASS: suppress_msg accepted
|
||||
PASS: unsuppress_msg accepted
|
||||
PASS: suppress_msg multiple IDs accepted
|
||||
PASS: unsuppress_msg multiple IDs accepted
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,17 @@
|
||||
# Test message suppress/unsuppress
|
||||
# suppress_msg and unsuppress_msg take message IDs as arguments
|
||||
|
||||
suppress_msg 999
|
||||
puts "PASS: suppress_msg accepted"
|
||||
|
||||
unsuppress_msg 999
|
||||
puts "PASS: unsuppress_msg accepted"
|
||||
|
||||
# Test with multiple IDs
|
||||
suppress_msg 100 200
|
||||
puts "PASS: suppress_msg multiple IDs accepted"
|
||||
|
||||
unsuppress_msg 100 200
|
||||
puts "PASS: unsuppress_msg multiple IDs accepted"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,273 @@
|
||||
--- thread operations ---
|
||||
initial thread_count: 1
|
||||
thread_count after set to 2: 2
|
||||
thread_count after set to 1: 1
|
||||
thread_count after set to 4: 4
|
||||
PASS: thread count operations
|
||||
--- processor_count ---
|
||||
processor_count: 64
|
||||
PASS: processor_count positive
|
||||
--- memory_usage ---
|
||||
PASS: memory_usage non-negative
|
||||
--- load design for parallel timing ---
|
||||
Warning: util_parallel_misc.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
Startpoint: data_a[6] (input port clocked by clk)
|
||||
Endpoint: carry (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v data_a[6] (in)
|
||||
0.06 0.06 v buf_a6/Z (BUF_X1)
|
||||
0.03 0.09 v and6/ZN (AND2_X1)
|
||||
0.05 0.13 v or_carry/ZN (OR2_X1)
|
||||
0.02 0.16 v buf_carry/Z (BUF_X1)
|
||||
0.00 0.16 v carry (out)
|
||||
0.16 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.16 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.84 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with 1 thread
|
||||
Startpoint: data_a[6] (input port clocked by clk)
|
||||
Endpoint: carry (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v data_a[6] (in)
|
||||
0.06 0.06 v buf_a6/Z (BUF_X1)
|
||||
0.03 0.09 v and6/ZN (AND2_X1)
|
||||
0.05 0.13 v or_carry/ZN (OR2_X1)
|
||||
0.02 0.16 v buf_carry/Z (BUF_X1)
|
||||
0.00 0.16 v carry (out)
|
||||
0.16 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.16 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.84 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with 2 threads
|
||||
Startpoint: data_a[6] (input port clocked by clk)
|
||||
Endpoint: carry (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v data_a[6] (in)
|
||||
0.06 0.06 v buf_a6/Z (BUF_X1)
|
||||
0.03 0.09 v and6/ZN (AND2_X1)
|
||||
0.05 0.13 v or_carry/ZN (OR2_X1)
|
||||
0.02 0.16 v buf_carry/Z (BUF_X1)
|
||||
0.00 0.16 v carry (out)
|
||||
0.16 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.16 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.84 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with 4 threads
|
||||
--- buffer growth test ---
|
||||
large capture length: 4827
|
||||
PASS: buffer growth
|
||||
--- string redirect large ---
|
||||
string redirect length: 4827
|
||||
PASS: string redirect large
|
||||
--- file redirect large ---
|
||||
file redirect size: 4827
|
||||
PASS: file redirect large
|
||||
--- append cycles ---
|
||||
appended file size: 2079
|
||||
PASS: append cycles
|
||||
--- debug with threads ---
|
||||
search: find arrivals pass 1
|
||||
search: find arrivals to level 90
|
||||
search: found 0 arrivals
|
||||
Startpoint: data_a[6] (input port clocked by clk)
|
||||
Endpoint: carry (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v data_a[6] (in)
|
||||
0.06 0.06 v buf_a6/Z (BUF_X1)
|
||||
0.03 0.09 v and6/ZN (AND2_X1)
|
||||
0.05 0.13 v or_carry/ZN (OR2_X1)
|
||||
0.02 0.16 v buf_carry/Z (BUF_X1)
|
||||
0.00 0.16 v carry (out)
|
||||
0.16 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.16 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.84 slack (MET)
|
||||
|
||||
|
||||
PASS: debug search with threads
|
||||
delay_calc: find delays to level 90
|
||||
delay_calc: found 0 delays
|
||||
Startpoint: data_a[6] (input port clocked by clk)
|
||||
Endpoint: carry (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v data_a[6] (in)
|
||||
0.06 0.06 v buf_a6/Z (BUF_X1)
|
||||
0.03 0.09 v and6/ZN (AND2_X1)
|
||||
0.05 0.13 v or_carry/ZN (OR2_X1)
|
||||
0.02 0.16 v buf_carry/Z (BUF_X1)
|
||||
0.00 0.16 v carry (out)
|
||||
0.16 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.16 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.84 slack (MET)
|
||||
|
||||
|
||||
PASS: debug delay_calc with threads
|
||||
--- report_line coverage ---
|
||||
|
||||
single line
|
||||
line with special: [ ] { } $ \
|
||||
very long line: abcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghij
|
||||
PASS: report_line coverage
|
||||
--- format extreme values ---
|
||||
format_time(1fs): 0.000000
|
||||
format_time(1ms): 1000000.062
|
||||
format_capacitance(1aF): 0.001000
|
||||
format_resistance(1mOhm): 0.000000
|
||||
format_power(1pW): 0.001000
|
||||
format_distance(1nm): 0.001000
|
||||
PASS: format extreme values
|
||||
--- log with design ops ---
|
||||
Startpoint: data_a[6] (input port clocked by clk)
|
||||
Endpoint: carry (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v data_a[6] (in)
|
||||
0.06 0.06 v buf_a6/Z (BUF_X1)
|
||||
0.03 0.09 v and6/ZN (AND2_X1)
|
||||
0.05 0.13 v or_carry/ZN (OR2_X1)
|
||||
0.02 0.16 v buf_carry/Z (BUF_X1)
|
||||
0.00 0.16 v carry (out)
|
||||
0.16 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.16 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.84 slack (MET)
|
||||
|
||||
|
||||
Startpoint: data_b[0] (input port clocked by clk)
|
||||
Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ data_b[0] (in)
|
||||
0.04 0.04 ^ and0/ZN (AND2_X1)
|
||||
0.00 0.04 ^ reg0/D (DFF_X1)
|
||||
0.04 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg0/CK (DFF_X1)
|
||||
0.01 0.01 library hold time
|
||||
0.01 data required time
|
||||
---------------------------------------------------------
|
||||
0.01 data required time
|
||||
-0.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.04 slack (MET)
|
||||
|
||||
|
||||
time 1ns
|
||||
capacitance 1fF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
PASS: log with design ops
|
||||
--- error paths ---
|
||||
PASS: caught nonexistent liberty error
|
||||
PASS: caught nonexistent verilog error
|
||||
PASS: caught nonexistent SPEF error
|
||||
PASS: caught nonexistent SDF error
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,257 @@
|
||||
# Test parallel dispatch, thread operations, and miscellaneous util coverage
|
||||
# Targets: DispatchQueue.cc (dispatch queue creation, parallel execution)
|
||||
# TokenParser.cc (token parsing operations)
|
||||
# Report.cc (printToBuffer growth, printToBufferAppend, various warn paths)
|
||||
# ReportTcl.cc (Tcl-specific report formatting and error paths)
|
||||
# MachineLinux.cc (thread count, processor count, memory usage)
|
||||
# StringUtil.cc (string operations)
|
||||
# Debug.cc (additional debug paths)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Thread count and parallel settings
|
||||
#---------------------------------------------------------------
|
||||
puts "--- thread operations ---"
|
||||
set tc [sta::thread_count]
|
||||
puts "initial thread_count: $tc"
|
||||
|
||||
# Set thread count to test dispatch queue paths
|
||||
sta::set_thread_count 2
|
||||
set tc2 [sta::thread_count]
|
||||
puts "thread_count after set to 2: $tc2"
|
||||
|
||||
sta::set_thread_count 1
|
||||
set tc3 [sta::thread_count]
|
||||
puts "thread_count after set to 1: $tc3"
|
||||
|
||||
# Try larger thread count
|
||||
sta::set_thread_count 4
|
||||
set tc4 [sta::thread_count]
|
||||
puts "thread_count after set to 4: $tc4"
|
||||
|
||||
# Reset to 1
|
||||
sta::set_thread_count 1
|
||||
puts "PASS: thread count operations"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Processor count
|
||||
#---------------------------------------------------------------
|
||||
puts "--- processor_count ---"
|
||||
set nproc [sta::processor_count]
|
||||
puts "processor_count: $nproc"
|
||||
if { $nproc > 0 } {
|
||||
puts "PASS: processor_count positive"
|
||||
} else {
|
||||
puts "FAIL: processor_count non-positive"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Memory usage
|
||||
#---------------------------------------------------------------
|
||||
puts "--- memory_usage ---"
|
||||
set mem [sta::memory_usage]
|
||||
if { $mem >= 0 } {
|
||||
puts "PASS: memory_usage non-negative"
|
||||
} else {
|
||||
puts "FAIL: memory_usage negative"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load a design to exercise parallel timing with threads
|
||||
#---------------------------------------------------------------
|
||||
puts "--- load design for parallel timing ---"
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog ../../verilog/test/verilog_complex_bus_test.v
|
||||
link_design verilog_complex_bus_test
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [all_inputs]
|
||||
set_output_delay -clock clk 0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
# Run timing with 1 thread
|
||||
sta::set_thread_count 1
|
||||
report_checks
|
||||
puts "PASS: report_checks with 1 thread"
|
||||
|
||||
# Run timing with 2 threads to exercise dispatch queue
|
||||
sta::set_thread_count 2
|
||||
report_checks
|
||||
puts "PASS: report_checks with 2 threads"
|
||||
|
||||
# Run timing with 4 threads
|
||||
sta::set_thread_count 4
|
||||
report_checks
|
||||
puts "PASS: report_checks with 4 threads"
|
||||
|
||||
# Back to 1
|
||||
sta::set_thread_count 1
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report redirect to variable multiple times (exercises buffer growth)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- buffer growth test ---"
|
||||
# Capture large output to exercise buffer growth paths
|
||||
with_output_to_variable v1 {
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_checks -path_delay max
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
}
|
||||
puts "large capture length: [string length $v1]"
|
||||
puts "PASS: buffer growth"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# String redirect with large content
|
||||
#---------------------------------------------------------------
|
||||
puts "--- string redirect large ---"
|
||||
sta::redirect_string_begin
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_checks -path_delay max
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
set s1 [sta::redirect_string_end]
|
||||
puts "string redirect length: [string length $s1]"
|
||||
puts "PASS: string redirect large"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report to file with large content
|
||||
#---------------------------------------------------------------
|
||||
puts "--- file redirect large ---"
|
||||
set rfile [make_result_file "util_parallel_redir.txt"]
|
||||
sta::redirect_file_begin $rfile
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_checks -path_delay max
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
sta::redirect_file_end
|
||||
if { [file exists $rfile] } {
|
||||
set fh [open $rfile r]
|
||||
set content [read $fh]
|
||||
close $fh
|
||||
puts "file redirect size: [string length $content]"
|
||||
puts "PASS: file redirect large"
|
||||
} else {
|
||||
puts "INFO: file not created"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report append with multiple cycles
|
||||
#---------------------------------------------------------------
|
||||
puts "--- append cycles ---"
|
||||
set afile [make_result_file "util_parallel_append.txt"]
|
||||
sta::redirect_file_begin $afile
|
||||
report_units
|
||||
sta::redirect_file_end
|
||||
|
||||
sta::redirect_file_append_begin $afile
|
||||
report_checks
|
||||
sta::redirect_file_end
|
||||
|
||||
sta::redirect_file_append_begin $afile
|
||||
report_checks -path_delay min
|
||||
sta::redirect_file_end
|
||||
|
||||
if { [file exists $afile] } {
|
||||
set fh [open $afile r]
|
||||
set content [read $fh]
|
||||
close $fh
|
||||
puts "appended file size: [string length $content]"
|
||||
puts "PASS: append cycles"
|
||||
} else {
|
||||
puts "INFO: append file not created"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Debug with parallel timing
|
||||
#---------------------------------------------------------------
|
||||
puts "--- debug with threads ---"
|
||||
sta::set_thread_count 2
|
||||
sta::set_debug "search" 1
|
||||
report_checks
|
||||
sta::set_debug "search" 0
|
||||
puts "PASS: debug search with threads"
|
||||
|
||||
sta::set_debug "delay_calc" 1
|
||||
report_checks
|
||||
sta::set_debug "delay_calc" 0
|
||||
puts "PASS: debug delay_calc with threads"
|
||||
|
||||
sta::set_thread_count 1
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Various report_line calls
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_line coverage ---"
|
||||
sta::report_line ""
|
||||
sta::report_line "single line"
|
||||
sta::report_line "line with special: \[ \] \{ \} \$ \\"
|
||||
sta::report_line "very long line: [string repeat "abcdefghij" 50]"
|
||||
puts "PASS: report_line coverage"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Format functions with extreme values
|
||||
#---------------------------------------------------------------
|
||||
puts "--- format extreme values ---"
|
||||
set ft_tiny [sta::format_time "1e-15" 6]
|
||||
puts "format_time(1fs): $ft_tiny"
|
||||
|
||||
set ft_huge [sta::format_time "1e-3" 3]
|
||||
puts "format_time(1ms): $ft_huge"
|
||||
|
||||
set fc_tiny [sta::format_capacitance "1e-18" 6]
|
||||
puts "format_capacitance(1aF): $fc_tiny"
|
||||
|
||||
set fr_tiny [sta::format_resistance "0.001" 6]
|
||||
puts "format_resistance(1mOhm): $fr_tiny"
|
||||
|
||||
set fp_tiny [sta::format_power "1e-12" 6]
|
||||
puts "format_power(1pW): $fp_tiny"
|
||||
|
||||
set fd_tiny [sta::format_distance "1e-9" 6]
|
||||
puts "format_distance(1nm): $fd_tiny"
|
||||
|
||||
puts "PASS: format extreme values"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Log file with design operations
|
||||
#---------------------------------------------------------------
|
||||
puts "--- log with design ops ---"
|
||||
set lfile [make_result_file "util_parallel_log.txt"]
|
||||
log_begin $lfile
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_units
|
||||
log_end
|
||||
if { [file exists $lfile] } {
|
||||
puts "PASS: log with design ops"
|
||||
} else {
|
||||
puts "INFO: log file not created"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Error paths (run last since they may affect design state)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- error paths ---"
|
||||
set rc [catch { read_liberty "/nonexistent/path/file.lib" } msg]
|
||||
if { $rc != 0 } {
|
||||
puts "PASS: caught nonexistent liberty error"
|
||||
}
|
||||
|
||||
set rc [catch { read_verilog "/nonexistent/path/file.v" } msg]
|
||||
if { $rc != 0 } {
|
||||
puts "PASS: caught nonexistent verilog error"
|
||||
}
|
||||
|
||||
set rc [catch { read_spef "/nonexistent/path/file.spef" } msg]
|
||||
if { $rc != 0 } {
|
||||
puts "PASS: caught nonexistent SPEF error"
|
||||
}
|
||||
|
||||
set rc [catch { read_sdf "/nonexistent/path/file.sdf" } msg]
|
||||
if { $rc != 0 } {
|
||||
puts "PASS: caught nonexistent SDF error"
|
||||
}
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,439 @@
|
||||
--- get_cells with wildcard * ---
|
||||
buf* cells: 1
|
||||
PASS: get_cells wildcard *
|
||||
--- get_cells with ? wildcard ---
|
||||
buf? cells: 1
|
||||
PASS: get_cells wildcard ?
|
||||
--- get_cells exact match ---
|
||||
buf1 cells: 1
|
||||
PASS: get_cells exact match
|
||||
--- get_cells * ---
|
||||
* cells: 3
|
||||
PASS: get_cells *
|
||||
--- get_pins with wildcards ---
|
||||
buf1/* pins: 2
|
||||
PASS: get_pins wildcard
|
||||
buf1/? pins: 2
|
||||
PASS: get_pins ? wildcard
|
||||
*/* pins: 10
|
||||
PASS: get_pins */*
|
||||
--- get_ports with wildcards ---
|
||||
*1 ports: 2
|
||||
PASS: get_ports wildcard
|
||||
* ports: 3
|
||||
PASS: get_ports *
|
||||
--- get_nets with wildcards ---
|
||||
n* nets: 2
|
||||
PASS: get_nets wildcard
|
||||
--- non-matching patterns ---
|
||||
Warning: util_pattern_string.tcl line 1, instance 'zzz_nonexistent' not found.
|
||||
get_cells nonexistent: rc=0
|
||||
PASS: non-matching pattern
|
||||
Warning: util_pattern_string.tcl line 1, pin 'zzz_nonexistent/*' not found.
|
||||
get_pins nonexistent: rc=0
|
||||
PASS: non-matching pin pattern
|
||||
--- get_lib_cells with wildcards ---
|
||||
BUF* lib_cells: 6
|
||||
PASS: get_lib_cells wildcard
|
||||
DFF_X? lib_cells: 2
|
||||
PASS: get_lib_cells ? wildcard
|
||||
* lib_cells: 134
|
||||
PASS: get_lib_cells *
|
||||
--- set_debug with level > 0 ---
|
||||
PASS: set_debug multiple modules
|
||||
delay_calc: delays invalid
|
||||
delay_calc: find delays to level 50
|
||||
delay_calc: found 9 delays
|
||||
search: find arrivals pass 1
|
||||
search: find arrivals to level 50
|
||||
search: arrival seed clk clk pin clk
|
||||
search: arrival seed input arrival in1
|
||||
search: find arrivals buf1/A
|
||||
search: in1
|
||||
search: ^ -> ^ min
|
||||
search: from tag: 4 ^ min/0 clk ^ clk_src clk crpr_pin null input in1
|
||||
search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.000 = 0.000 < MIA
|
||||
search: in1
|
||||
search: ^ -> ^ max
|
||||
search: from tag: 6 ^ max/1 clk ^ clk_src clk crpr_pin null input in1
|
||||
search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.000 = 0.000 > MIA
|
||||
search: in1
|
||||
search: v -> v min
|
||||
search: from tag: 5 v min/0 clk ^ clk_src clk crpr_pin null input in1
|
||||
search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.000 = 0.000 < MIA
|
||||
search: in1
|
||||
search: v -> v max
|
||||
search: from tag: 7 v max/1 clk ^ clk_src clk crpr_pin null input in1
|
||||
search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.000 = 0.000 > MIA
|
||||
search: find arrivals reg1/CK
|
||||
search: clk
|
||||
search: ^ -> ^ min
|
||||
search: from tag: 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.000 = 0.000 < MIA
|
||||
search: clk
|
||||
search: ^ -> ^ max
|
||||
search: from tag: 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.000 = 0.000 > MIA
|
||||
search: clk
|
||||
search: v -> v min
|
||||
search: from tag: 1 v min/0 clk v (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 1 v min/0 clk v (clock ideal) clk_src clk crpr_pin null
|
||||
search: 5.000 + 0.000 = 5.000 < MIA
|
||||
search: clk
|
||||
search: v -> v max
|
||||
search: from tag: 3 v max/1 clk v (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 3 v max/1 clk v (clock ideal) clk_src clk crpr_pin null
|
||||
search: 5.000 + 0.000 = 5.000 > MIA
|
||||
search: find arrivals reg1/Q
|
||||
search: reg1/CK
|
||||
search: ^ -> ^ min
|
||||
search: from tag: 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.081 = 0.081 < MIA
|
||||
search: reg1/CK
|
||||
search: ^ -> v min
|
||||
search: from tag: 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.075 = 0.075 < MIA
|
||||
search: reg1/CK
|
||||
search: ^ -> ^ max
|
||||
search: from tag: 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.081 = 0.081 > MIA
|
||||
search: reg1/CK
|
||||
search: ^ -> v max
|
||||
search: from tag: 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.075 = 0.075 > MIA
|
||||
search: find arrivals reg1/QN
|
||||
search: reg1/CK
|
||||
search: ^ -> ^ min
|
||||
search: from tag: 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.056 = 0.056 < MIA
|
||||
search: reg1/CK
|
||||
search: ^ -> v min
|
||||
search: from tag: 0 ^ min/0 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.057 = 0.057 < MIA
|
||||
search: reg1/CK
|
||||
search: ^ -> ^ max
|
||||
search: from tag: 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.056 = 0.056 > MIA
|
||||
search: reg1/CK
|
||||
search: ^ -> v max
|
||||
search: from tag: 2 ^ max/1 clk ^ (clock ideal) clk_src clk crpr_pin null
|
||||
search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.057 = 0.057 > MIA
|
||||
search: find arrivals buf1/Z
|
||||
search: buf1/A
|
||||
search: ^ -> ^ min
|
||||
search: from tag: 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.018 = 0.018 < MIA
|
||||
search: buf1/A
|
||||
search: ^ -> ^ max
|
||||
search: from tag: 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.018 = 0.018 > MIA
|
||||
search: buf1/A
|
||||
search: v -> v min
|
||||
search: from tag: 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.022 = 0.022 < MIA
|
||||
search: buf1/A
|
||||
search: v -> v max
|
||||
search: from tag: 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.000 + 0.022 = 0.022 > MIA
|
||||
search: find arrivals inv1/A
|
||||
search: buf1/Z
|
||||
search: ^ -> ^ min
|
||||
search: from tag: 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.018 + 0.000 = 0.018 < MIA
|
||||
search: buf1/Z
|
||||
search: ^ -> ^ max
|
||||
search: from tag: 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.018 + 0.000 = 0.018 > MIA
|
||||
search: buf1/Z
|
||||
search: v -> v min
|
||||
search: from tag: 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.022 + 0.000 = 0.022 < MIA
|
||||
search: buf1/Z
|
||||
search: v -> v max
|
||||
search: from tag: 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.022 + 0.000 = 0.022 > MIA
|
||||
search: find arrivals out1
|
||||
search: reg1/Q
|
||||
search: ^ -> ^ min
|
||||
search: from tag: 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.081 + 0.000 = 0.081 < MIA
|
||||
search: reg1/Q
|
||||
search: ^ -> ^ max
|
||||
search: from tag: 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.081 + 0.000 = 0.081 > MIA
|
||||
search: reg1/Q
|
||||
search: v -> v min
|
||||
search: from tag: 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.075 + 0.000 = 0.075 < MIA
|
||||
search: reg1/Q
|
||||
search: v -> v max
|
||||
search: from tag: 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.075 + 0.000 = 0.075 > MIA
|
||||
search: find arrivals inv1/ZN
|
||||
search: inv1/A
|
||||
search: ^ -> v min
|
||||
search: from tag: 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.018 + 0.006 = 0.024 < MIA
|
||||
search: inv1/A
|
||||
search: ^ -> v max
|
||||
search: from tag: 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.018 + 0.006 = 0.024 > MIA
|
||||
search: inv1/A
|
||||
search: v -> ^ min
|
||||
search: from tag: 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.022 + 0.010 = 0.032 < MIA
|
||||
search: inv1/A
|
||||
search: v -> ^ max
|
||||
search: from tag: 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.022 + 0.010 = 0.032 > MIA
|
||||
search: find arrivals reg1/D
|
||||
search: inv1/ZN
|
||||
search: ^ -> ^ min
|
||||
search: from tag: 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 8 ^ min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.032 + 0.000 = 0.032 < MIA
|
||||
search: inv1/ZN
|
||||
search: ^ -> ^ max
|
||||
search: from tag: 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 9 ^ max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.032 + 0.000 = 0.032 > MIA
|
||||
search: inv1/ZN
|
||||
search: v -> v min
|
||||
search: from tag: 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 10 v min/0 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.024 + 0.000 = 0.024 < MIA
|
||||
search: inv1/ZN
|
||||
search: v -> v max
|
||||
search: from tag: 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: to tag : 11 v max/1 clk ^ clk_src clk crpr_pin null
|
||||
search: 0.024 + 0.000 = 0.024 > MIA
|
||||
search: found 9 arrivals
|
||||
search: find end slack reg1/D
|
||||
search: find end slack reg1/QN
|
||||
search: find end slack out1
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with debug on
|
||||
PASS: set_debug all off
|
||||
--- FileNotWritable error path ---
|
||||
PASS: caught FileNotWritable for bad path
|
||||
PASS: caught error for unwritable log path
|
||||
--- report_checks with rise/fall fields ---
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.88 0.15 0.00 0.00 v in1 (in)
|
||||
1.55 0.01 0.07 0.07 v buf1/Z (BUF_X1)
|
||||
1.14 0.01 0.01 0.08 ^ inv1/ZN (INV_X1)
|
||||
0.01 0.00 0.08 ^ reg1/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
-----------------------------------------------------------------------
|
||||
9.97 data required time
|
||||
-0.08 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
9.89 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with rise/fall transitions
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.97 0.20 0.00 0.00 ^ in1 (in)
|
||||
0.20 0.00 0.00 ^ buf1/A (BUF_X1)
|
||||
1.70 0.01 0.03 0.03 ^ buf1/Z (BUF_X1)
|
||||
0.01 0.00 0.03 ^ inv1/A (INV_X1)
|
||||
1.06 0.00 0.01 0.04 v inv1/ZN (INV_X1)
|
||||
0.00 0.00 0.04 v reg1/D (DFF_X1)
|
||||
0.04 data arrival time
|
||||
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
-----------------------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.04 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
0.04 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks min with fields
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.88 0.15 0.00 0.00 v in1 (in)
|
||||
0.15 0.00 0.00 v buf1/A (BUF_X1)
|
||||
1.55 0.01 0.07 0.07 v buf1/Z (BUF_X1)
|
||||
0.01 0.00 0.07 v inv1/A (INV_X1)
|
||||
1.14 0.01 0.01 0.08 ^ inv1/ZN (INV_X1)
|
||||
0.01 0.00 0.08 ^ reg1/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
-----------------------------------------------------------------------
|
||||
9.97 data required time
|
||||
-0.08 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
9.89 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks max with fields
|
||||
--- set_load rise/fall ---
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in1 (in)
|
||||
0.07 0.07 v buf1/Z (BUF_X1)
|
||||
0.01 0.08 ^ inv1/ZN (INV_X1)
|
||||
0.00 0.08 ^ reg1/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.89 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with min/max loads
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in1 (in)
|
||||
0.07 0.07 v buf1/Z (BUF_X1)
|
||||
0.01 0.08 ^ inv1/ZN (INV_X1)
|
||||
0.00 0.08 ^ reg1/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.89 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with rise/fall min/max loads
|
||||
--- with_output_to_variable nesting ---
|
||||
v1 captured 984 chars
|
||||
PASS: with_output_to_variable
|
||||
v2 captured 1967 chars
|
||||
PASS: with_output_to_variable multiple reports
|
||||
--- redirect_string with reports ---
|
||||
redirect string: 1414 chars
|
||||
PASS: redirect_string with full report
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,204 @@
|
||||
# Test pattern matching edge cases and string utility coverage
|
||||
# Targets: PatternMatch.cc (52.3% -> wildcards, nocase, regexp paths)
|
||||
# Debug.cc (43.5% -> debug level set/check, stats level)
|
||||
# Stats.cc (52.0% -> stats reporting with debug on)
|
||||
# StringUtil.cc (84.6% -> string formatting edge cases)
|
||||
# Error.cc (60.0% -> FileNotWritable, ExceptionLine)
|
||||
# RiseFallValues.cc (45.0%)
|
||||
# RiseFallMinMax.cc (69.7%)
|
||||
# Transition.cc (81.8%)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# PatternMatch.cc coverage via get_cells/get_pins wildcards
|
||||
#---------------------------------------------------------------
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog ../../dcalc/test/dcalc_test1.v
|
||||
link_design dcalc_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
|
||||
# Wildcard pattern matching: '*' at end
|
||||
puts "--- get_cells with wildcard * ---"
|
||||
set cells_star [get_cells buf*]
|
||||
puts "buf* cells: [llength $cells_star]"
|
||||
puts "PASS: get_cells wildcard *"
|
||||
|
||||
# Wildcard: '?' single char
|
||||
puts "--- get_cells with ? wildcard ---"
|
||||
set cells_q [get_cells buf?]
|
||||
puts "buf? cells: [llength $cells_q]"
|
||||
puts "PASS: get_cells wildcard ?"
|
||||
|
||||
# Wildcard: exact match (no wildcards)
|
||||
puts "--- get_cells exact match ---"
|
||||
set cells_exact [get_cells buf1]
|
||||
puts "buf1 cells: [llength $cells_exact]"
|
||||
puts "PASS: get_cells exact match"
|
||||
|
||||
# Wildcard: '*' matching everything
|
||||
puts "--- get_cells * ---"
|
||||
set cells_all [get_cells *]
|
||||
puts "* cells: [llength $cells_all]"
|
||||
puts "PASS: get_cells *"
|
||||
|
||||
# get_pins with wildcards
|
||||
puts "--- get_pins with wildcards ---"
|
||||
set pins_star [get_pins buf1/*]
|
||||
puts "buf1/* pins: [llength $pins_star]"
|
||||
puts "PASS: get_pins wildcard"
|
||||
|
||||
set pins_q [get_pins buf1/?]
|
||||
puts "buf1/? pins: [llength $pins_q]"
|
||||
puts "PASS: get_pins ? wildcard"
|
||||
|
||||
set pins_all [get_pins */*]
|
||||
puts "*/* pins: [llength $pins_all]"
|
||||
puts "PASS: get_pins */*"
|
||||
|
||||
# get_ports with wildcards
|
||||
puts "--- get_ports with wildcards ---"
|
||||
set ports_star [get_ports *1]
|
||||
puts "*1 ports: [llength $ports_star]"
|
||||
puts "PASS: get_ports wildcard"
|
||||
|
||||
set ports_all [get_ports *]
|
||||
puts "* ports: [llength $ports_all]"
|
||||
puts "PASS: get_ports *"
|
||||
|
||||
# get_nets with wildcards
|
||||
puts "--- get_nets with wildcards ---"
|
||||
set nets_star [get_nets n*]
|
||||
puts "n* nets: [llength $nets_star]"
|
||||
puts "PASS: get_nets wildcard"
|
||||
|
||||
# Pattern that matches nothing
|
||||
puts "--- non-matching patterns ---"
|
||||
set rc [catch {get_cells zzz_nonexistent} msg]
|
||||
puts "get_cells nonexistent: rc=$rc"
|
||||
puts "PASS: non-matching pattern"
|
||||
|
||||
set rc [catch {get_pins zzz_nonexistent/*} msg]
|
||||
puts "get_pins nonexistent: rc=$rc"
|
||||
puts "PASS: non-matching pin pattern"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# get_lib_cells with wildcards (exercises PatternMatch::match)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- get_lib_cells with wildcards ---"
|
||||
set lc1 [get_lib_cells NangateOpenCellLibrary/BUF*]
|
||||
puts "BUF* lib_cells: [llength $lc1]"
|
||||
puts "PASS: get_lib_cells wildcard"
|
||||
|
||||
set lc2 [get_lib_cells NangateOpenCellLibrary/DFF_X?]
|
||||
puts "DFF_X? lib_cells: [llength $lc2]"
|
||||
puts "PASS: get_lib_cells ? wildcard"
|
||||
|
||||
set lc3 [get_lib_cells NangateOpenCellLibrary/*]
|
||||
puts "* lib_cells: [llength $lc3]"
|
||||
puts "PASS: get_lib_cells *"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Debug.cc coverage: set_debug with various levels, stats
|
||||
#---------------------------------------------------------------
|
||||
puts "--- set_debug with level > 0 ---"
|
||||
sta::set_debug "search" 3
|
||||
sta::set_debug "graph" 2
|
||||
sta::set_debug "delay_calc" 1
|
||||
puts "PASS: set_debug multiple modules"
|
||||
|
||||
# Trigger debug check path by running timing with debug on
|
||||
report_checks
|
||||
puts "PASS: report_checks with debug on"
|
||||
|
||||
# Turn off debug levels
|
||||
sta::set_debug "search" 0
|
||||
sta::set_debug "graph" 0
|
||||
sta::set_debug "delay_calc" 0
|
||||
puts "PASS: set_debug all off"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Error.cc: FileNotWritable path
|
||||
#---------------------------------------------------------------
|
||||
puts "--- FileNotWritable error path ---"
|
||||
set rc [catch { write_sdf "/nonexistent_dir/no_write.sdf" } msg]
|
||||
if { $rc != 0 } {
|
||||
puts "PASS: caught FileNotWritable for bad path"
|
||||
} else {
|
||||
puts "INFO: no error for bad write path"
|
||||
}
|
||||
|
||||
# Try write to read-only path
|
||||
set rc [catch { log_begin "/proc/nonexistent_log" } msg]
|
||||
if { $rc != 0 } {
|
||||
puts "PASS: caught error for unwritable log path"
|
||||
} else {
|
||||
log_end
|
||||
puts "INFO: log_begin succeeded on /proc path"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Transition.cc coverage: rise/fall operations
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with rise/fall fields ---"
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
set_input_transition 0.2 [get_ports in1] -rise
|
||||
set_input_transition 0.15 [get_ports in1] -fall
|
||||
report_checks -fields {slew cap}
|
||||
puts "PASS: report_checks with rise/fall transitions"
|
||||
|
||||
report_checks -path_delay min -fields {slew cap input_pins}
|
||||
puts "PASS: report_checks min with fields"
|
||||
|
||||
report_checks -path_delay max -fields {slew cap input_pins}
|
||||
puts "PASS: report_checks max with fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# RiseFallMinMax / RiseFallValues coverage
|
||||
#---------------------------------------------------------------
|
||||
puts "--- set_load rise/fall ---"
|
||||
set_load -min 0.05 [get_ports out1]
|
||||
set_load -max 0.1 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: report_checks with min/max loads"
|
||||
|
||||
set_load -rise -min 0.02 [get_ports out1]
|
||||
set_load -fall -min 0.03 [get_ports out1]
|
||||
set_load -rise -max 0.08 [get_ports out1]
|
||||
set_load -fall -max 0.09 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: report_checks with rise/fall min/max loads"
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# with_output_to_variable with nested calls
|
||||
#---------------------------------------------------------------
|
||||
puts "--- with_output_to_variable nesting ---"
|
||||
with_output_to_variable v1 {
|
||||
report_checks
|
||||
}
|
||||
puts "v1 captured [string length $v1] chars"
|
||||
puts "PASS: with_output_to_variable"
|
||||
|
||||
with_output_to_variable v2 {
|
||||
report_checks -path_delay min
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "v2 captured [string length $v2] chars"
|
||||
puts "PASS: with_output_to_variable multiple reports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Redirect string with content
|
||||
#---------------------------------------------------------------
|
||||
puts "--- redirect_string with reports ---"
|
||||
sta::redirect_string_begin
|
||||
report_checks -fields {slew cap input_pins}
|
||||
set rstr [sta::redirect_string_end]
|
||||
puts "redirect string: [string length $rstr] chars"
|
||||
puts "PASS: redirect_string with full report"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,203 @@
|
||||
--- redirect + log simultaneously ---
|
||||
redirect file size: 1961
|
||||
PASS: redirect + log simultaneously
|
||||
log file size: 1961
|
||||
PASS: log file has content
|
||||
--- gzipped liberty read ---
|
||||
Warning: ../../test/nangate45/nangate45_typ.lib.gz line 37, library NangateOpenCellLibrary already exists.
|
||||
PASS: read gzipped liberty
|
||||
--- trigger warn paths ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.32 0.32 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.32 ^ out1 (out)
|
||||
0.32 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.32 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.68 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with extreme load
|
||||
--- debug check path coverage ---
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
delay_calc: find delays to level 50
|
||||
delay_calc: find delays reg1/Q (DFF_X1)
|
||||
delay_calc: find delays out1 (dcalc_test1)
|
||||
delay_calc: found 2 delays
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
delay_calc: find delays to level 50
|
||||
delay_calc: found 0 delays
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
dcalc with debug: done
|
||||
PASS: report_dcalc with debug on
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with levelize debug
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with bfs debug
|
||||
--- multiple redirect cycles ---
|
||||
PASS: multiple redirect cycles
|
||||
--- string redirect cycles ---
|
||||
s1 len: 95
|
||||
s2 len: 883
|
||||
s3 len: 1866
|
||||
PASS: string redirect cycles
|
||||
--- report_line coverage ---
|
||||
|
||||
test line 1
|
||||
test line with special chars: [ ] { }
|
||||
PASS: report_line coverage
|
||||
--- format functions edge cases ---
|
||||
format_time(0): 0.000
|
||||
format_time(-1ns): -1.000
|
||||
format_time(1us, 6 digits): 1000.000000
|
||||
format_capacitance(0): 0.000
|
||||
format_capacitance(1nF): 999999.938
|
||||
format_resistance(0): 0.000
|
||||
format_resistance(1MOhm): 1000.000
|
||||
format_power(0): 0.000
|
||||
format_power(1W): 1000000000.000
|
||||
PASS: format functions edge cases
|
||||
--- set_cmd_units edge cases ---
|
||||
time 1ps
|
||||
capacitance 1fF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
time 1us
|
||||
capacitance 1fF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
PASS: set_cmd_units time edge cases
|
||||
PASS: set_cmd_units capacitance edge cases
|
||||
PASS: set_cmd_units resistance edge cases
|
||||
PASS: set_cmd_units distance edge cases
|
||||
PASS: set_cmd_units power edge cases
|
||||
PASS: set_cmd_units current edge cases
|
||||
PASS: set_cmd_units voltage edge cases
|
||||
--- suppress_msg exercising suppressed check ---
|
||||
PASS: suppress_msg many IDs
|
||||
PASS: unsuppress_msg many IDs
|
||||
PASS: suppress/unsuppress single
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,257 @@
|
||||
# Test Report.cc formatting edge cases, Debug.cc check paths,
|
||||
# and various report output destinations.
|
||||
# Targets: Report.cc (69.8% -> warn, fileWarn, printToBufferAppend grow)
|
||||
# ReportTcl.cc (69.4% -> Tcl-specific report paths)
|
||||
# Debug.cc (43.5% -> debug check/level, reportLine)
|
||||
# StringUtil.cc (84.6% -> trimRight, stringPrint, etc.)
|
||||
# MinMax.cc (83.9% -> min/max index operations)
|
||||
# gzstream.hh (77.9% -> gz read/write operations)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog ../../dcalc/test/dcalc_test1.v
|
||||
link_design dcalc_test1
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report redirect to file + log simultaneously
|
||||
#---------------------------------------------------------------
|
||||
puts "--- redirect + log simultaneously ---"
|
||||
set log_file [make_result_file "util_debug_log.txt"]
|
||||
set redir_file [make_result_file "util_debug_redir.txt"]
|
||||
|
||||
log_begin $log_file
|
||||
sta::redirect_file_begin $redir_file
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_units
|
||||
sta::redirect_file_end
|
||||
log_end
|
||||
|
||||
if { [file exists $redir_file] } {
|
||||
set fh [open $redir_file r]
|
||||
set content [read $fh]
|
||||
close $fh
|
||||
puts "redirect file size: [string length $content]"
|
||||
puts "PASS: redirect + log simultaneously"
|
||||
} else {
|
||||
puts "INFO: redirect file not created"
|
||||
}
|
||||
|
||||
if { [file exists $log_file] } {
|
||||
set fh [open $log_file r]
|
||||
set content [read $fh]
|
||||
close $fh
|
||||
puts "log file size: [string length $content]"
|
||||
puts "PASS: log file has content"
|
||||
} else {
|
||||
puts "INFO: log file not created"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# gzstream: Read/write gzipped liberty
|
||||
#---------------------------------------------------------------
|
||||
puts "--- gzipped liberty read ---"
|
||||
set rc [catch { read_liberty ../../test/nangate45/nangate45_typ.lib.gz } msg]
|
||||
if { $rc == 0 } {
|
||||
puts "PASS: read gzipped liberty"
|
||||
} else {
|
||||
puts "INFO: gzipped liberty read: $msg"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report warn path (triggered by warnings in design analysis)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- trigger warn paths ---"
|
||||
# Set very large load to trigger potential warnings
|
||||
set_load 100.0 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: report_checks with extreme load"
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Debug: enable and verify paths with timing analysis
|
||||
#---------------------------------------------------------------
|
||||
puts "--- debug check path coverage ---"
|
||||
sta::set_debug "delay_calc" 2
|
||||
|
||||
# report_dcalc with debug on exercises debug check/reportLine paths
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "dcalc with debug: done"
|
||||
puts "PASS: report_dcalc with debug on"
|
||||
|
||||
sta::set_debug "delay_calc" 0
|
||||
|
||||
# Debug with levelization
|
||||
sta::set_debug "levelize" 1
|
||||
report_checks
|
||||
puts "PASS: report_checks with levelize debug"
|
||||
sta::set_debug "levelize" 0
|
||||
|
||||
# Debug with bfs
|
||||
sta::set_debug "bfs" 1
|
||||
report_checks
|
||||
puts "PASS: report_checks with bfs debug"
|
||||
sta::set_debug "bfs" 0
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multiple redirect/log open/close cycles
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multiple redirect cycles ---"
|
||||
set f1 [make_result_file "util_redir1.txt"]
|
||||
set f2 [make_result_file "util_redir2.txt"]
|
||||
set f3 [make_result_file "util_redir3.txt"]
|
||||
|
||||
# Cycle 1
|
||||
sta::redirect_file_begin $f1
|
||||
report_units
|
||||
sta::redirect_file_end
|
||||
|
||||
# Cycle 2
|
||||
sta::redirect_file_begin $f2
|
||||
report_checks
|
||||
sta::redirect_file_end
|
||||
|
||||
# Cycle 3 - append
|
||||
sta::redirect_file_append_begin $f2
|
||||
report_checks -path_delay min
|
||||
sta::redirect_file_end
|
||||
|
||||
# Cycle 4
|
||||
sta::redirect_file_begin $f3
|
||||
report_checks -fields {slew cap input_pins}
|
||||
sta::redirect_file_end
|
||||
|
||||
puts "PASS: multiple redirect cycles"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# String redirect multiple times
|
||||
#---------------------------------------------------------------
|
||||
puts "--- string redirect cycles ---"
|
||||
sta::redirect_string_begin
|
||||
report_units
|
||||
set s1 [sta::redirect_string_end]
|
||||
|
||||
sta::redirect_string_begin
|
||||
report_checks
|
||||
set s2 [sta::redirect_string_end]
|
||||
|
||||
sta::redirect_string_begin
|
||||
report_checks -path_delay min
|
||||
report_checks -path_delay max
|
||||
set s3 [sta::redirect_string_end]
|
||||
|
||||
puts "s1 len: [string length $s1]"
|
||||
puts "s2 len: [string length $s2]"
|
||||
puts "s3 len: [string length $s3]"
|
||||
puts "PASS: string redirect cycles"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report blank line and reportLineString paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_line coverage ---"
|
||||
sta::report_line ""
|
||||
sta::report_line "test line 1"
|
||||
sta::report_line "test line with special chars: \[ \] \{ \}"
|
||||
puts "PASS: report_line coverage"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# format_* functions with edge values
|
||||
#---------------------------------------------------------------
|
||||
puts "--- format functions edge cases ---"
|
||||
set ft0 [sta::format_time "0" 3]
|
||||
puts "format_time(0): $ft0"
|
||||
|
||||
set ft_neg [sta::format_time "-1e-9" 3]
|
||||
puts "format_time(-1ns): $ft_neg"
|
||||
|
||||
set ft_large [sta::format_time "1e-6" 6]
|
||||
puts "format_time(1us, 6 digits): $ft_large"
|
||||
|
||||
set fc0 [sta::format_capacitance "0" 3]
|
||||
puts "format_capacitance(0): $fc0"
|
||||
|
||||
set fc_large [sta::format_capacitance "1e-9" 3]
|
||||
puts "format_capacitance(1nF): $fc_large"
|
||||
|
||||
set fr0 [sta::format_resistance "0" 3]
|
||||
puts "format_resistance(0): $fr0"
|
||||
|
||||
set fr_large [sta::format_resistance "1e6" 3]
|
||||
puts "format_resistance(1MOhm): $fr_large"
|
||||
|
||||
set fp0 [sta::format_power "0" 3]
|
||||
puts "format_power(0): $fp0"
|
||||
|
||||
set fp_large [sta::format_power "1.0" 3]
|
||||
puts "format_power(1W): $fp_large"
|
||||
|
||||
puts "PASS: format functions edge cases"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_cmd_units with various suffix combinations
|
||||
#---------------------------------------------------------------
|
||||
puts "--- set_cmd_units edge cases ---"
|
||||
set_cmd_units -time ps
|
||||
report_units
|
||||
set_cmd_units -time us
|
||||
report_units
|
||||
set_cmd_units -time ns
|
||||
puts "PASS: set_cmd_units time edge cases"
|
||||
|
||||
set_cmd_units -capacitance pF
|
||||
set_cmd_units -capacitance fF
|
||||
set_cmd_units -capacitance pF
|
||||
puts "PASS: set_cmd_units capacitance edge cases"
|
||||
|
||||
set_cmd_units -resistance Ohm
|
||||
set_cmd_units -resistance kOhm
|
||||
puts "PASS: set_cmd_units resistance edge cases"
|
||||
|
||||
set_cmd_units -distance nm
|
||||
set_cmd_units -distance um
|
||||
set_cmd_units -distance mm
|
||||
set_cmd_units -distance um
|
||||
puts "PASS: set_cmd_units distance edge cases"
|
||||
|
||||
set_cmd_units -power nW
|
||||
set_cmd_units -power uW
|
||||
set_cmd_units -power mW
|
||||
set_cmd_units -power W
|
||||
set_cmd_units -power mW
|
||||
puts "PASS: set_cmd_units power edge cases"
|
||||
|
||||
set_cmd_units -current uA
|
||||
set_cmd_units -current mA
|
||||
set_cmd_units -current A
|
||||
set_cmd_units -current mA
|
||||
puts "PASS: set_cmd_units current edge cases"
|
||||
|
||||
set_cmd_units -voltage mV
|
||||
set_cmd_units -voltage V
|
||||
puts "PASS: set_cmd_units voltage edge cases"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# suppress/unsuppress with actual message IDs
|
||||
#---------------------------------------------------------------
|
||||
puts "--- suppress_msg exercising suppressed check ---"
|
||||
suppress_msg 1 2 3 4 5 6 7 8 9 10
|
||||
suppress_msg 100 200 300 400 500
|
||||
puts "PASS: suppress_msg many IDs"
|
||||
|
||||
# Unsuppress all
|
||||
unsuppress_msg 1 2 3 4 5 6 7 8 9 10
|
||||
unsuppress_msg 100 200 300 400 500
|
||||
puts "PASS: unsuppress_msg many IDs"
|
||||
|
||||
# Suppress then trigger a warning by doing something that warns
|
||||
suppress_msg 100
|
||||
unsuppress_msg 100
|
||||
puts "PASS: suppress/unsuppress single"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,125 @@
|
||||
--- unit format sequences ---
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
PASS: ns/pF/kOhm
|
||||
time 1us
|
||||
capacitance 1nF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
PASS: us/nF
|
||||
time 1ps
|
||||
capacitance 1fF
|
||||
resistance 1ohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
PASS: ps/fF/Ohm
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
PASS: back to ns/pF/kOhm
|
||||
--- format functions edge cases ---
|
||||
format_time 0: 0.000
|
||||
format_time 1e-9: 1.000
|
||||
format_time 1e-12: 0.001000
|
||||
format_time 1e-6: 1000.000
|
||||
PASS: format_time
|
||||
format_cap 0: 0.000
|
||||
format_cap 1e-12: 1.000
|
||||
format_cap 1e-15: 0.001000
|
||||
PASS: format_capacitance
|
||||
format_res 0: 0.000
|
||||
format_res 1000: 1.000
|
||||
format_res 1e6: 1000.000
|
||||
PASS: format_resistance
|
||||
format_volt 0: 0.000
|
||||
format_volt 1.1: 1.100
|
||||
format_volt 0.001: 0.001000
|
||||
PASS: format_voltage
|
||||
format_curr 0: 0.000
|
||||
format_curr 1e-3: 0.001
|
||||
format_curr 1e-6: 0.000000
|
||||
PASS: format_current
|
||||
format_pwr 0: 0.000
|
||||
format_pwr 1e-3: 0.001
|
||||
format_pwr 1e-9: 0.000000
|
||||
PASS: format_power
|
||||
format_dist 0: 0.000
|
||||
format_dist 1e-6: 0.000
|
||||
format_dist 1e-3: 0.001000
|
||||
PASS: format_distance
|
||||
--- redirect sequences ---
|
||||
redirect string 1: 92 chars
|
||||
redirect string 2: 92 chars
|
||||
redirect string 3: 184 chars
|
||||
PASS: redirect sequences
|
||||
--- with_output_to_variable ---
|
||||
v1: 92 chars
|
||||
v2: 18 chars
|
||||
v3: 92 chars
|
||||
PASS: with_output_to_variable
|
||||
--- log file ---
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
time 1ps
|
||||
capacitance 1fF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
PASS: log file with reports
|
||||
PASS: log file has content
|
||||
--- redirect file append ---
|
||||
PASS: redirect file append
|
||||
PASS: redirect file has content
|
||||
--- error handling ---
|
||||
PASS: FileNotReadable caught
|
||||
PASS: FileNotReadable for verilog caught
|
||||
--- fuzzy equal ---
|
||||
fuzzy_equal(1.0, 1.0) = 1
|
||||
fuzzy_equal(1.0, 2.0) = 0
|
||||
fuzzy_equal(0.0, 0.0) = 1
|
||||
fuzzy_equal(1e-15, 1e-15) = 1
|
||||
PASS: fuzzy_equal
|
||||
--- is_object ---
|
||||
is_object(string) = 0
|
||||
PASS: is_object
|
||||
--- system info ---
|
||||
PASS: thread_count positive
|
||||
PASS: processor_count positive
|
||||
PASS: memory_usage non-negative
|
||||
PASS: cputime non-negative
|
||||
PASS: elapsed non-negative
|
||||
PASS: user_run_time non-negative
|
||||
PASS: system info
|
||||
--- debug ---
|
||||
PASS: debug level
|
||||
--- suppress ---
|
||||
PASS: suppress/unsuppress
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,233 @@
|
||||
# Test util report formatting, error paths, string operations
|
||||
# Targets: Report.cc (printConsole, printLine, printString, reportLine,
|
||||
# reportLineString, warn, error, vfileWarn, vfileError, redirect paths,
|
||||
# logBegin/logEnd, buffer management)
|
||||
# Targets: TokenParser.cc (hasNext/next parsing)
|
||||
# Targets: StringUtil.cc (stdstrPrint, trimRight, isSame patterns)
|
||||
# Targets: Error.cc (FileNotReadable, FileNotWritable, InternalError)
|
||||
# Targets: PatternMatch.cc (various match operations)
|
||||
# Targets: MachineLinux.cc (readMemoryUsage, readCpuTime)
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report formatting with different unit scales
|
||||
#---------------------------------------------------------------
|
||||
puts "--- unit format sequences ---"
|
||||
set_cmd_units -time ns -capacitance pF -resistance kOhm
|
||||
report_units
|
||||
puts "PASS: ns/pF/kOhm"
|
||||
|
||||
set_cmd_units -time us -capacitance nF
|
||||
report_units
|
||||
puts "PASS: us/nF"
|
||||
|
||||
set_cmd_units -time ps -capacitance fF -resistance Ohm
|
||||
report_units
|
||||
puts "PASS: ps/fF/Ohm"
|
||||
|
||||
set_cmd_units -time ns -capacitance pF -resistance kOhm
|
||||
report_units
|
||||
puts "PASS: back to ns/pF/kOhm"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Format functions with different values
|
||||
#---------------------------------------------------------------
|
||||
puts "--- format functions edge cases ---"
|
||||
puts "format_time 0: [sta::format_time 0 3]"
|
||||
puts "format_time 1e-9: [sta::format_time 1e-9 3]"
|
||||
puts "format_time 1e-12: [sta::format_time 1e-12 6]"
|
||||
puts "format_time 1e-6: [sta::format_time 1e-6 3]"
|
||||
puts "PASS: format_time"
|
||||
|
||||
puts "format_cap 0: [sta::format_capacitance 0 3]"
|
||||
puts "format_cap 1e-12: [sta::format_capacitance 1e-12 3]"
|
||||
puts "format_cap 1e-15: [sta::format_capacitance 1e-15 6]"
|
||||
puts "PASS: format_capacitance"
|
||||
|
||||
puts "format_res 0: [sta::format_resistance 0 3]"
|
||||
puts "format_res 1000: [sta::format_resistance 1000 3]"
|
||||
puts "format_res 1e6: [sta::format_resistance 1e6 3]"
|
||||
puts "PASS: format_resistance"
|
||||
|
||||
puts "format_volt 0: [sta::format_voltage 0 3]"
|
||||
puts "format_volt 1.1: [sta::format_voltage 1.1 3]"
|
||||
puts "format_volt 0.001: [sta::format_voltage 0.001 6]"
|
||||
puts "PASS: format_voltage"
|
||||
|
||||
puts "format_curr 0: [sta::format_current 0 3]"
|
||||
puts "format_curr 1e-3: [sta::format_current 1e-3 3]"
|
||||
puts "format_curr 1e-6: [sta::format_current 1e-6 6]"
|
||||
puts "PASS: format_current"
|
||||
|
||||
puts "format_pwr 0: [sta::format_power 0 3]"
|
||||
puts "format_pwr 1e-3: [sta::format_power 1e-3 3]"
|
||||
puts "format_pwr 1e-9: [sta::format_power 1e-9 6]"
|
||||
puts "PASS: format_power"
|
||||
|
||||
puts "format_dist 0: [sta::format_distance 0 3]"
|
||||
puts "format_dist 1e-6: [sta::format_distance 1e-6 3]"
|
||||
puts "format_dist 1e-3: [sta::format_distance 1e-3 6]"
|
||||
puts "PASS: format_distance"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multiple redirect sequences (exercises buffer management)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- redirect sequences ---"
|
||||
sta::redirect_string_begin
|
||||
report_units
|
||||
set r1 [sta::redirect_string_end]
|
||||
puts "redirect string 1: [string length $r1] chars"
|
||||
|
||||
sta::redirect_string_begin
|
||||
set_cmd_units -time ps
|
||||
report_units
|
||||
set r2 [sta::redirect_string_end]
|
||||
puts "redirect string 2: [string length $r2] chars"
|
||||
|
||||
sta::redirect_string_begin
|
||||
set_cmd_units -time ns
|
||||
report_units
|
||||
set_cmd_units -capacitance pF
|
||||
report_units
|
||||
set r3 [sta::redirect_string_end]
|
||||
puts "redirect string 3: [string length $r3] chars"
|
||||
puts "PASS: redirect sequences"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# with_output_to_variable
|
||||
#---------------------------------------------------------------
|
||||
puts "--- with_output_to_variable ---"
|
||||
with_output_to_variable v1 { report_units }
|
||||
with_output_to_variable v2 { puts "line1"; puts "line2"; puts "line3" }
|
||||
with_output_to_variable v3 { set_cmd_units -time ps; report_units }
|
||||
puts "v1: [string length $v1] chars"
|
||||
puts "v2: [string length $v2] chars"
|
||||
puts "v3: [string length $v3] chars"
|
||||
set_cmd_units -time ns
|
||||
puts "PASS: with_output_to_variable"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Log file with multiple reports
|
||||
#---------------------------------------------------------------
|
||||
puts "--- log file ---"
|
||||
set log_file [make_result_file "util_format_log.txt"]
|
||||
log_begin $log_file
|
||||
report_units
|
||||
set_cmd_units -time ps -capacitance fF
|
||||
report_units
|
||||
set_cmd_units -time ns -capacitance pF
|
||||
report_units
|
||||
log_end
|
||||
puts "PASS: log file with reports"
|
||||
|
||||
if { [file exists $log_file] } {
|
||||
set fh [open $log_file r]
|
||||
set lc [read $fh]
|
||||
close $fh
|
||||
if { [string length $lc] > 0 } { puts "PASS: log file has content" }
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Redirect file with append
|
||||
#---------------------------------------------------------------
|
||||
puts "--- redirect file append ---"
|
||||
set rf [make_result_file "util_format_redir.txt"]
|
||||
sta::redirect_file_begin $rf
|
||||
report_units
|
||||
sta::redirect_file_end
|
||||
|
||||
sta::redirect_file_append_begin $rf
|
||||
set_cmd_units -time ps -capacitance fF
|
||||
report_units
|
||||
sta::redirect_file_end
|
||||
|
||||
sta::redirect_file_append_begin $rf
|
||||
set_cmd_units -time ns -capacitance pF
|
||||
report_units
|
||||
sta::redirect_file_end
|
||||
|
||||
puts "PASS: redirect file append"
|
||||
|
||||
if { [file exists $rf] } {
|
||||
set fh [open $rf r]
|
||||
set rc [read $fh]
|
||||
close $fh
|
||||
if { [string length $rc] > 0 } { puts "PASS: redirect file has content" }
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Error handling paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- error handling ---"
|
||||
set rc [catch { read_liberty "/nonexistent/path/test.lib" } msg]
|
||||
if { $rc != 0 } {
|
||||
puts "PASS: FileNotReadable caught"
|
||||
}
|
||||
|
||||
set rc [catch { read_verilog "/nonexistent/path/test.v" } msg]
|
||||
if { $rc != 0 } {
|
||||
puts "PASS: FileNotReadable for verilog caught"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Fuzzy equality
|
||||
#---------------------------------------------------------------
|
||||
puts "--- fuzzy equal ---"
|
||||
puts "fuzzy_equal(1.0, 1.0) = [sta::fuzzy_equal 1.0 1.0]"
|
||||
puts "fuzzy_equal(1.0, 2.0) = [sta::fuzzy_equal 1.0 2.0]"
|
||||
puts "fuzzy_equal(0.0, 0.0) = [sta::fuzzy_equal 0.0 0.0]"
|
||||
puts "fuzzy_equal(1e-15, 1e-15) = [sta::fuzzy_equal 1e-15 1e-15]"
|
||||
puts "PASS: fuzzy_equal"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Object type queries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- is_object ---"
|
||||
puts "is_object(string) = [sta::is_object not_an_object]"
|
||||
puts "PASS: is_object"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Thread and system info
|
||||
#---------------------------------------------------------------
|
||||
puts "--- system info ---"
|
||||
set tc [sta::thread_count]
|
||||
if { $tc > 0 } { puts "PASS: thread_count positive" }
|
||||
|
||||
set np [sta::processor_count]
|
||||
if { $np > 0 } { puts "PASS: processor_count positive" }
|
||||
|
||||
set mem [sta::memory_usage]
|
||||
if { $mem >= 0 } { puts "PASS: memory_usage non-negative" }
|
||||
|
||||
set cpu [sta::cputime]
|
||||
if { $cpu >= 0 } { puts "PASS: cputime non-negative" }
|
||||
|
||||
set elapsed [elapsed_run_time]
|
||||
if { $elapsed >= 0 } { puts "PASS: elapsed non-negative" }
|
||||
|
||||
set utime [user_run_time]
|
||||
if { $utime >= 0 } { puts "PASS: user_run_time non-negative" }
|
||||
puts "PASS: system info"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Debug level
|
||||
#---------------------------------------------------------------
|
||||
puts "--- debug ---"
|
||||
sta::set_debug "search" 1
|
||||
sta::set_debug "search" 0
|
||||
sta::set_debug "graph" 1
|
||||
sta::set_debug "graph" 0
|
||||
sta::set_debug "delay_calc" 1
|
||||
sta::set_debug "delay_calc" 0
|
||||
puts "PASS: debug level"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Message suppression
|
||||
#---------------------------------------------------------------
|
||||
puts "--- suppress ---"
|
||||
suppress_msg 100 200 300 400 500
|
||||
unsuppress_msg 100 200 300 400 500
|
||||
puts "PASS: suppress/unsuppress"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,2 @@
|
||||
--- processor_count ---
|
||||
Error: util_report_redirect.tcl, 11 invalid command name "processor_count"
|
||||
@@ -0,0 +1,105 @@
|
||||
--- processor_count ---
|
||||
PASS: processor_count returned 64
|
||||
--- memory_usage ---
|
||||
PASS: memory_usage returned non-negative value
|
||||
--- elapsed_run_time ---
|
||||
PASS: elapsed_run_time returned non-negative value
|
||||
--- user_run_time ---
|
||||
PASS: user_run_time returned non-negative value
|
||||
--- cputime ---
|
||||
PASS: cputime returned non-negative value
|
||||
--- redirect to file ---
|
||||
PASS: redirect_file_begin/end completed
|
||||
PASS: redirect file has content
|
||||
--- redirect append to file ---
|
||||
PASS: redirect_file_append_begin/end completed
|
||||
PASS: appended redirect file has content
|
||||
--- log_begin with content ---
|
||||
time 1s
|
||||
capacitance 1F
|
||||
resistance 1ohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
time 1ps
|
||||
capacitance 1fF
|
||||
resistance 1ohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1ohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
PASS: log_begin/log_end with reports
|
||||
PASS: log file has report content
|
||||
--- FileNotReadable error path ---
|
||||
PASS: caught expected error for nonexistent file
|
||||
--- with_output_to_variable multiple calls ---
|
||||
captured v1 length: 91
|
||||
captured v2 length: 12
|
||||
captured v3 length: 97
|
||||
PASS: multiple with_output_to_variable calls
|
||||
--- redirect_string_begin/end ---
|
||||
redirect string captured: 91 chars
|
||||
PASS: redirect_string_begin/end
|
||||
--- set_cmd_units power ---
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1ohm
|
||||
voltage 1v
|
||||
current 1A
|
||||
power 1W
|
||||
distance 1m
|
||||
PASS: set_cmd_units -power mW
|
||||
--- set_cmd_units all options ---
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1W
|
||||
distance 1um
|
||||
PASS: set_cmd_units all options
|
||||
--- set_debug commands ---
|
||||
PASS: set_debug search on/off
|
||||
PASS: set_debug graph on/off
|
||||
--- suppress/unsuppress variety ---
|
||||
PASS: suppress/unsuppress variety
|
||||
--- thread_count ---
|
||||
thread_count: 1
|
||||
PASS: thread_count
|
||||
--- fuzzy_equal ---
|
||||
fuzzy_equal(1.0, 1.0) = 1
|
||||
fuzzy_equal(1.0, 2.0) = 0
|
||||
PASS: fuzzy_equal
|
||||
--- is_object ---
|
||||
is_object(not_an_object) = 0
|
||||
PASS: is_object
|
||||
--- format_time ---
|
||||
format_time: 1.000
|
||||
PASS: format_time
|
||||
--- format_capacitance ---
|
||||
format_capacitance: 1.000
|
||||
PASS: format_capacitance
|
||||
--- format_resistance ---
|
||||
format_resistance: 1.000
|
||||
PASS: format_resistance
|
||||
--- format_voltage ---
|
||||
format_voltage: 1.100
|
||||
PASS: format_voltage
|
||||
--- format_current ---
|
||||
format_current: 1.000
|
||||
PASS: format_current
|
||||
--- format_power ---
|
||||
format_power: 0.001
|
||||
PASS: format_power
|
||||
--- format_distance ---
|
||||
format_distance: 1.000
|
||||
PASS: format_distance
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,260 @@
|
||||
# Test util report formatting, log file handling, and redirect paths
|
||||
# Targets uncovered lines in Report.cc, ReportTcl.cc, MachineLinux.cc,
|
||||
# Debug.cc, PatternMatch.cc, StringUtil.cc, Error.cc
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Memory/CPU reporting (MachineLinux.cc coverage)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- processor_count ---"
|
||||
set nproc [sta::processor_count]
|
||||
if { $nproc > 0 } {
|
||||
puts "PASS: processor_count returned $nproc"
|
||||
} else {
|
||||
puts "FAIL: processor_count returned $nproc"
|
||||
}
|
||||
|
||||
puts "--- memory_usage ---"
|
||||
set mem [sta::memory_usage]
|
||||
if { $mem >= 0 } {
|
||||
puts "PASS: memory_usage returned non-negative value"
|
||||
} else {
|
||||
puts "FAIL: memory_usage returned negative"
|
||||
}
|
||||
|
||||
puts "--- elapsed_run_time ---"
|
||||
set elapsed [elapsed_run_time]
|
||||
if { $elapsed >= 0 } {
|
||||
puts "PASS: elapsed_run_time returned non-negative value"
|
||||
} else {
|
||||
puts "FAIL: elapsed_run_time returned negative"
|
||||
}
|
||||
|
||||
puts "--- user_run_time ---"
|
||||
set user_time [user_run_time]
|
||||
if { $user_time >= 0 } {
|
||||
puts "PASS: user_run_time returned non-negative value"
|
||||
} else {
|
||||
puts "FAIL: user_run_time returned negative"
|
||||
}
|
||||
|
||||
puts "--- cputime ---"
|
||||
set cput [sta::cputime]
|
||||
if { $cput >= 0 } {
|
||||
puts "PASS: cputime returned non-negative value"
|
||||
} else {
|
||||
puts "FAIL: cputime returned negative"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report redirect to file (Report.cc redirectFileBegin/End)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- redirect to file ---"
|
||||
set redir_file [make_result_file "util_redirect_out.txt"]
|
||||
sta::redirect_file_begin $redir_file
|
||||
puts "redirected content line 1"
|
||||
report_units
|
||||
sta::redirect_file_end
|
||||
puts "PASS: redirect_file_begin/end completed"
|
||||
|
||||
if { [file exists $redir_file] } {
|
||||
set fh [open $redir_file r]
|
||||
set content [read $fh]
|
||||
close $fh
|
||||
if { [string length $content] > 0 } {
|
||||
puts "PASS: redirect file has content"
|
||||
} else {
|
||||
puts "INFO: redirect file was empty"
|
||||
}
|
||||
} else {
|
||||
puts "INFO: redirect file not found"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Redirect append to file (Report.cc redirectFileAppendBegin)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- redirect append to file ---"
|
||||
set append_file [make_result_file "util_redirect_append.txt"]
|
||||
sta::redirect_file_begin $append_file
|
||||
puts "first write"
|
||||
sta::redirect_file_end
|
||||
|
||||
sta::redirect_file_append_begin $append_file
|
||||
puts "appended content"
|
||||
sta::redirect_file_end
|
||||
puts "PASS: redirect_file_append_begin/end completed"
|
||||
|
||||
if { [file exists $append_file] } {
|
||||
set fh [open $append_file r]
|
||||
set content [read $fh]
|
||||
close $fh
|
||||
if { [string length $content] > 0 } {
|
||||
puts "PASS: appended redirect file has content"
|
||||
} else {
|
||||
puts "INFO: appended redirect file was empty"
|
||||
}
|
||||
} else {
|
||||
puts "INFO: appended redirect file not found"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Log file operations (Report.cc logBegin/logEnd, ReportTcl.cc)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- log_begin with content ---"
|
||||
set log_file2 [make_result_file "util_log2.txt"]
|
||||
log_begin $log_file2
|
||||
report_units
|
||||
set_cmd_units -time ps -capacitance fF
|
||||
report_units
|
||||
set_cmd_units -time ns -capacitance pF
|
||||
report_units
|
||||
log_end
|
||||
puts "PASS: log_begin/log_end with reports"
|
||||
|
||||
if { [file exists $log_file2] } {
|
||||
set fh [open $log_file2 r]
|
||||
set log_content [read $fh]
|
||||
close $fh
|
||||
if { [string length $log_content] > 0 } {
|
||||
puts "PASS: log file has report content"
|
||||
} else {
|
||||
puts "INFO: log file was empty (may be expected)"
|
||||
}
|
||||
} else {
|
||||
puts "INFO: log file not found (may be expected)"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Error handling paths (Error.cc, FileNotReadable)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- FileNotReadable error path ---"
|
||||
set rc [catch { read_liberty "/nonexistent/file/path.lib" } msg]
|
||||
if { $rc != 0 } {
|
||||
puts "PASS: caught expected error for nonexistent file"
|
||||
} else {
|
||||
puts "INFO: no error for nonexistent file"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# with_output_to_variable (redirect string path in Report.cc)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- with_output_to_variable multiple calls ---"
|
||||
with_output_to_variable v1 { report_units }
|
||||
with_output_to_variable v2 { puts "hello world" }
|
||||
with_output_to_variable v3 { report_units; puts "extra" }
|
||||
puts "captured v1 length: [string length $v1]"
|
||||
puts "captured v2 length: [string length $v2]"
|
||||
puts "captured v3 length: [string length $v3]"
|
||||
puts "PASS: multiple with_output_to_variable calls"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Redirect string directly (exercises redirect string paths)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- redirect_string_begin/end ---"
|
||||
sta::redirect_string_begin
|
||||
report_units
|
||||
set rstr [sta::redirect_string_end]
|
||||
puts "redirect string captured: [string length $rstr] chars"
|
||||
puts "PASS: redirect_string_begin/end"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Unit commands (various set_cmd_units options)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- set_cmd_units power ---"
|
||||
set_cmd_units -power mW
|
||||
report_units
|
||||
puts "PASS: set_cmd_units -power mW"
|
||||
|
||||
puts "--- set_cmd_units all options ---"
|
||||
set_cmd_units -time ns -capacitance pF -resistance kOhm -voltage V -current mA -distance um -power mW
|
||||
report_units
|
||||
puts "PASS: set_cmd_units all options"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Debug level setting (Debug.cc)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- set_debug commands ---"
|
||||
sta::set_debug "search" 1
|
||||
sta::set_debug "search" 0
|
||||
puts "PASS: set_debug search on/off"
|
||||
|
||||
sta::set_debug "graph" 2
|
||||
sta::set_debug "graph" 0
|
||||
puts "PASS: set_debug graph on/off"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Message suppression exercising different paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- suppress/unsuppress variety ---"
|
||||
suppress_msg 1 2 3 4 5
|
||||
unsuppress_msg 1 2 3 4 5
|
||||
suppress_msg 999
|
||||
unsuppress_msg 999
|
||||
puts "PASS: suppress/unsuppress variety"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Thread count
|
||||
#---------------------------------------------------------------
|
||||
puts "--- thread_count ---"
|
||||
set tc [sta::thread_count]
|
||||
puts "thread_count: $tc"
|
||||
puts "PASS: thread_count"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Fuzzy equality
|
||||
#---------------------------------------------------------------
|
||||
puts "--- fuzzy_equal ---"
|
||||
set eq1 [sta::fuzzy_equal 1.0 1.0]
|
||||
set eq2 [sta::fuzzy_equal 1.0 2.0]
|
||||
puts "fuzzy_equal(1.0, 1.0) = $eq1"
|
||||
puts "fuzzy_equal(1.0, 2.0) = $eq2"
|
||||
puts "PASS: fuzzy_equal"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# is_object / object_type
|
||||
#---------------------------------------------------------------
|
||||
puts "--- is_object ---"
|
||||
set io1 [sta::is_object "not_an_object"]
|
||||
puts "is_object(not_an_object) = $io1"
|
||||
puts "PASS: is_object"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Unit format functions
|
||||
#---------------------------------------------------------------
|
||||
puts "--- format_time ---"
|
||||
set ft [sta::format_time "1e-9" 3]
|
||||
puts "format_time: $ft"
|
||||
puts "PASS: format_time"
|
||||
|
||||
puts "--- format_capacitance ---"
|
||||
set fc [sta::format_capacitance "1e-12" 3]
|
||||
puts "format_capacitance: $fc"
|
||||
puts "PASS: format_capacitance"
|
||||
|
||||
puts "--- format_resistance ---"
|
||||
set fr [sta::format_resistance "1000" 3]
|
||||
puts "format_resistance: $fr"
|
||||
puts "PASS: format_resistance"
|
||||
|
||||
puts "--- format_voltage ---"
|
||||
set fv [sta::format_voltage "1.1" 3]
|
||||
puts "format_voltage: $fv"
|
||||
puts "PASS: format_voltage"
|
||||
|
||||
puts "--- format_current ---"
|
||||
set fi [sta::format_current "1e-3" 3]
|
||||
puts "format_current: $fi"
|
||||
puts "PASS: format_current"
|
||||
|
||||
puts "--- format_power ---"
|
||||
set fp [sta::format_power "1e-3" 3]
|
||||
puts "format_power: $fp"
|
||||
puts "PASS: format_power"
|
||||
|
||||
puts "--- format_distance ---"
|
||||
set fd [sta::format_distance "1e-6" 3]
|
||||
puts "format_distance: $fd"
|
||||
puts "PASS: format_distance"
|
||||
|
||||
puts "ALL PASSED"
|
||||
@@ -0,0 +1,379 @@
|
||||
--- Test 1: log file with large output ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ r2/CK (DFF_X1)
|
||||
0.08 0.08 v r2/Q (DFF_X1)
|
||||
0.02 0.10 v u1/Z (BUF_X1)
|
||||
0.03 0.13 v u2/ZN (AND2_X1)
|
||||
0.00 0.13 v r3/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ r3/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in1 (in)
|
||||
0.00 0.00 v r1/D (DFF_X1)
|
||||
0.00 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ r1/CK (DFF_X1)
|
||||
0.05 0.05 library hold time
|
||||
0.05 data required time
|
||||
---------------------------------------------------------
|
||||
0.05 data required time
|
||||
-0.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
-0.05 slack (VIOLATED)
|
||||
|
||||
|
||||
Warning: util_report_string_log.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ r2/CK (DFF_X1)
|
||||
1 0.88 0.01 0.08 0.08 v r2/Q (DFF_X1)
|
||||
0.01 0.00 0.08 v u1/A (BUF_X1)
|
||||
1 0.89 0.00 0.02 0.10 v u1/Z (BUF_X1)
|
||||
0.00 0.00 0.10 v u2/A2 (AND2_X1)
|
||||
1 1.06 0.01 0.03 0.13 v u2/ZN (AND2_X1)
|
||||
0.01 0.00 0.13 v r3/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ r3/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ r2/CK (DFF_X1)
|
||||
0.08 0.08 v r2/Q (DFF_X1)
|
||||
0.02 0.10 v u1/Z (BUF_X1)
|
||||
0.03 0.13 v u2/ZN (AND2_X1)
|
||||
0.00 0.13 v r3/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ r3/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ r2/CK (DFF_X1)
|
||||
0.08 0.08 v r2/Q (DFF_X1)
|
||||
0.02 0.10 v u1/Z (BUF_X1)
|
||||
0.03 0.13 v u2/ZN (AND2_X1)
|
||||
0.00 0.13 v r3/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ r3/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ r2/CK (DFF_X1)
|
||||
0.08 0.08 v r2/Q (DFF_X1)
|
||||
0.02 0.10 v u1/Z (BUF_X1)
|
||||
0.03 0.13 v u2/ZN (AND2_X1)
|
||||
0.00 0.13 v r3/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ r3/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ r2/CK (DFF_X1)
|
||||
0.08 0.08 v r2/Q (DFF_X1)
|
||||
0.02 0.10 v u1/Z (BUF_X1)
|
||||
0.03 0.13 v u2/ZN (AND2_X1)
|
||||
0.00 0.13 v r3/D (DFF_X1)
|
||||
0.13 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ r3/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.13 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.83 slack (MET)
|
||||
|
||||
|
||||
Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ r3/CK (DFF_X1)
|
||||
0.08 0.08 ^ r3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in1 (in)
|
||||
0.00 0.00 v r1/D (DFF_X1)
|
||||
0.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ r1/CK (DFF_X1)
|
||||
-0.07 9.93 library setup time
|
||||
9.93 data required time
|
||||
---------------------------------------------------------
|
||||
9.93 data required time
|
||||
-0.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.93 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.00 0.00 v r2/D (DFF_X1)
|
||||
0.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ r2/CK (DFF_X1)
|
||||
-0.07 9.93 library setup time
|
||||
9.93 data required time
|
||||
---------------------------------------------------------
|
||||
9.93 data required time
|
||||
-0.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.93 slack (MET)
|
||||
|
||||
|
||||
time 1ns
|
||||
capacitance 1fF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
time 1ps
|
||||
capacitance 1fF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
time 1ns
|
||||
capacitance 1pF
|
||||
resistance 1kohm
|
||||
voltage 1v
|
||||
current 1mA
|
||||
power 1nW
|
||||
distance 1um
|
||||
PASS: log file with large output
|
||||
log file size: 10600
|
||||
PASS: log file has significant content
|
||||
--- Test 2: log + redirect simultaneous ---
|
||||
PASS: simultaneous log + redirect
|
||||
log size: 3326, redirect size: 3326
|
||||
PASS: both files have content
|
||||
--- Test 3: redirect string ---
|
||||
redirect string length: 2002
|
||||
PASS: redirect string captured large content
|
||||
cycle 0 string length: 95
|
||||
cycle 1 string length: 95
|
||||
cycle 2 string length: 95
|
||||
cycle 3 string length: 95
|
||||
cycle 4 string length: 95
|
||||
PASS: redirect string cycles
|
||||
--- Test 4: with_output_to_variable ---
|
||||
v1 length: 994
|
||||
v2 length: 913
|
||||
v3 length: 95
|
||||
v4 length: 2002
|
||||
PASS: combined output >= single
|
||||
PASS: with_output_to_variable
|
||||
--- Test 5: redirect file append ---
|
||||
before append: 95, after append: 1089
|
||||
PASS: append grew file
|
||||
PASS: redirect file append
|
||||
--- Test 6: error paths ---
|
||||
PASS: caught FileNotReadable
|
||||
PASS: caught FileNotWritable
|
||||
Warning: /workspace/sta/OpenSTA/util/test/results/bad_verilog.v line 2, module NONEXISTENT_CELL not found. Creating black box for u1.
|
||||
bad verilog result: rc=0
|
||||
PASS: bad verilog error path
|
||||
--- Test 7: message suppression ---
|
||||
PASS: suppress range
|
||||
PASS: unsuppress range
|
||||
PASS: suppress SPEF warnings
|
||||
PASS: unsuppress SPEF warnings
|
||||
--- Test 8: debug levels ---
|
||||
PASS: debug level setting
|
||||
PASS: higher debug levels
|
||||
--- Test 9: format functions ---
|
||||
format_time(1e-9) = 1.0000
|
||||
format_time(1e-10) = 0.1000
|
||||
format_time(1e-11) = 0.0100
|
||||
format_time(1e-12) = 0.0010
|
||||
format_time(5.5e-9) = 5.5000
|
||||
format_time(0.0) = 0.0000
|
||||
format_capacitance(1e-12) = 1.0000
|
||||
format_capacitance(1e-13) = 0.1000
|
||||
format_capacitance(1e-14) = 0.0100
|
||||
format_capacitance(1e-15) = 0.0010
|
||||
format_capacitance(5.5e-12) = 5.5000
|
||||
format_capacitance(0.0) = 0.0000
|
||||
format_resistance(100) = 0.1000
|
||||
format_resistance(1000) = 1.0000
|
||||
format_resistance(10000) = 10.0000
|
||||
format_resistance(0.1) = 0.0001
|
||||
format_resistance(0.0) = 0.0000
|
||||
format_power(1e-3) = 1000000.0625
|
||||
format_power(1e-6) = 1000.0000
|
||||
format_power(1e-9) = 1.0000
|
||||
format_power(5.5e-3) = 5500000.0000
|
||||
format_power(0.0) = 0.0000
|
||||
PASS: format functions
|
||||
ALL PASSED
|
||||
@@ -0,0 +1,287 @@
|
||||
# Test Report.cc string output, log file, and buffer growth paths.
|
||||
# Targets: Report.cc uncovered:
|
||||
# reportBlankLine (line 102-105)
|
||||
# reportLineString (const char*) (line 108-111)
|
||||
# reportLineString (const std::string&) (line 114-117)
|
||||
# printToBuffer (non-varargs, line 122-129)
|
||||
# printToBufferAppend: buffer growth path (line 158-168)
|
||||
# printBufferLine (line 172-175)
|
||||
# vwarn (line 196-206): va_list warn variant
|
||||
# vfileWarn (line 227-239): va_list file warn variant
|
||||
# verror (line 256-263): va_list error variant
|
||||
# fileError (line 266-279)
|
||||
# vfileError (line 282-292)
|
||||
# logBegin / logEnd (line 348-362)
|
||||
# redirectFileBegin / redirectFileEnd (line 365-386)
|
||||
# redirectFileAppendBegin (line 373-378)
|
||||
# redirectStringBegin / redirectStringEnd / redirectStringPrint
|
||||
# Also targets: Debug.cc, PatternMatch.cc, StringUtil.cc
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Log file with extensive output to trigger buffer growth
|
||||
# Exercises: logBegin, logEnd, printToBufferAppend buffer growth
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: log file with large output ---"
|
||||
|
||||
set log1 [make_result_file "util_log_large.txt"]
|
||||
log_begin $log1
|
||||
|
||||
# Generate lots of output to exercise buffer
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog ../../examples/example1.v
|
||||
link_design top
|
||||
|
||||
create_clock -name clk -period 10 {clk1 clk2 clk3}
|
||||
set_input_delay -clock clk 0 {in1 in2}
|
||||
set_output_delay -clock clk 0 [get_ports out]
|
||||
set_input_transition 0.1 {in1 in2 clk1 clk2 clk3}
|
||||
|
||||
# Generate many timing reports (exercises printToBuffer extensively)
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -format full_clock_expanded
|
||||
report_checks -format full_clock
|
||||
report_checks -sort_by_slack
|
||||
report_checks -group_path_count 10
|
||||
|
||||
# Unit reports
|
||||
report_units
|
||||
set_cmd_units -time ps -capacitance fF
|
||||
report_units
|
||||
set_cmd_units -time ns -capacitance pF
|
||||
report_units
|
||||
set_cmd_units -time ns -capacitance pF -resistance kOhm -voltage V -current mA
|
||||
report_units
|
||||
|
||||
log_end
|
||||
puts "PASS: log file with large output"
|
||||
|
||||
# Verify log file was created and has content
|
||||
if { [file exists $log1] } {
|
||||
set sz [file size $log1]
|
||||
puts "log file size: $sz"
|
||||
if { $sz > 1000 } {
|
||||
puts "PASS: log file has significant content"
|
||||
}
|
||||
} else {
|
||||
puts "INFO: log file not created"
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Log + redirect simultaneously
|
||||
# Exercises: printString dual output path (redirect + log)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: log + redirect simultaneous ---"
|
||||
|
||||
set log2 [make_result_file "util_log_simul.txt"]
|
||||
set redir2 [make_result_file "util_redir_simul.txt"]
|
||||
|
||||
log_begin $log2
|
||||
sta::redirect_file_begin $redir2
|
||||
|
||||
# All output goes to both log and redirect
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_checks -fields {slew cap}
|
||||
report_units
|
||||
|
||||
sta::redirect_file_end
|
||||
log_end
|
||||
puts "PASS: simultaneous log + redirect"
|
||||
|
||||
if { [file exists $log2] && [file exists $redir2] } {
|
||||
set sz_log [file size $log2]
|
||||
set sz_redir [file size $redir2]
|
||||
puts "log size: $sz_log, redirect size: $sz_redir"
|
||||
if { $sz_log > 0 && $sz_redir > 0 } {
|
||||
puts "PASS: both files have content"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Redirect string with large content
|
||||
# Exercises: redirectStringBegin/End/Print, redirect_to_string_ path
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: redirect string ---"
|
||||
|
||||
sta::redirect_string_begin
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_units
|
||||
set str1 [sta::redirect_string_end]
|
||||
puts "redirect string length: [string length $str1]"
|
||||
if { [string length $str1] > 100 } {
|
||||
puts "PASS: redirect string captured large content"
|
||||
}
|
||||
|
||||
# Multiple redirect string cycles
|
||||
for {set i 0} {$i < 5} {incr i} {
|
||||
sta::redirect_string_begin
|
||||
report_units
|
||||
set s [sta::redirect_string_end]
|
||||
puts "cycle $i string length: [string length $s]"
|
||||
}
|
||||
puts "PASS: redirect string cycles"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: with_output_to_variable (exercises string redirect)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: with_output_to_variable ---"
|
||||
|
||||
with_output_to_variable v1 { report_checks }
|
||||
with_output_to_variable v2 { report_checks -path_delay min }
|
||||
with_output_to_variable v3 { report_units }
|
||||
with_output_to_variable v4 {
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_units
|
||||
}
|
||||
puts "v1 length: [string length $v1]"
|
||||
puts "v2 length: [string length $v2]"
|
||||
puts "v3 length: [string length $v3]"
|
||||
puts "v4 length: [string length $v4]"
|
||||
|
||||
if { [string length $v4] >= [string length $v1] } {
|
||||
puts "PASS: combined output >= single"
|
||||
}
|
||||
puts "PASS: with_output_to_variable"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Redirect file append
|
||||
# Exercises: redirectFileAppendBegin
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: redirect file append ---"
|
||||
|
||||
set app_file [make_result_file "util_append.txt"]
|
||||
|
||||
# First write
|
||||
sta::redirect_file_begin $app_file
|
||||
report_units
|
||||
sta::redirect_file_end
|
||||
|
||||
set sz_before [file size $app_file]
|
||||
|
||||
# Append
|
||||
sta::redirect_file_append_begin $app_file
|
||||
report_checks
|
||||
sta::redirect_file_end
|
||||
|
||||
set sz_after [file size $app_file]
|
||||
puts "before append: $sz_before, after append: $sz_after"
|
||||
if { $sz_after > $sz_before } {
|
||||
puts "PASS: append grew file"
|
||||
}
|
||||
puts "PASS: redirect file append"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Error handling paths
|
||||
# Exercises: error, fileError (via bad file reads)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: error paths ---"
|
||||
|
||||
# FileNotReadable
|
||||
set rc1 [catch { read_liberty "/nonexistent/path/xyz.lib" } err1]
|
||||
if { $rc1 != 0 } {
|
||||
puts "PASS: caught FileNotReadable"
|
||||
}
|
||||
|
||||
# FileNotWritable (try writing to /dev/null/impossible)
|
||||
set rc2 [catch { write_verilog "/nonexistent/dir/xyz.v" } err2]
|
||||
if { $rc2 != 0 } {
|
||||
puts "PASS: caught FileNotWritable"
|
||||
}
|
||||
|
||||
# Bad verilog file
|
||||
set bad_v [make_result_file "bad_verilog.v"]
|
||||
set fh [open $bad_v w]
|
||||
puts $fh "module bad_design (input a, output b);"
|
||||
puts $fh " NONEXISTENT_CELL u1 (.A(a), .Z(b));"
|
||||
puts $fh "endmodule"
|
||||
close $fh
|
||||
set rc3 [catch {
|
||||
read_verilog $bad_v
|
||||
link_design bad_design
|
||||
} err3]
|
||||
puts "bad verilog result: rc=$rc3"
|
||||
puts "PASS: bad verilog error path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Message suppression/unsuppression
|
||||
# Exercises: suppressMsgId, unsuppressMsgId, isSuppressed
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: message suppression ---"
|
||||
|
||||
# Suppress a range of message IDs
|
||||
for {set id 100} {$id < 120} {incr id} {
|
||||
suppress_msg $id
|
||||
}
|
||||
puts "PASS: suppress range"
|
||||
|
||||
# Unsuppress them
|
||||
for {set id 100} {$id < 120} {incr id} {
|
||||
unsuppress_msg $id
|
||||
}
|
||||
puts "PASS: unsuppress range"
|
||||
|
||||
# Suppress specific warnings
|
||||
suppress_msg 1640 1641 1642 1643 1644 1645
|
||||
puts "PASS: suppress SPEF warnings"
|
||||
|
||||
unsuppress_msg 1640 1641 1642 1643 1644 1645
|
||||
puts "PASS: unsuppress SPEF warnings"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 8: Debug level setting
|
||||
# Exercises: Debug.cc set/check paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 8: debug levels ---"
|
||||
|
||||
foreach tag {search graph delay_calc parasitic_reduce verilog} {
|
||||
sta::set_debug $tag 1
|
||||
sta::set_debug $tag 0
|
||||
}
|
||||
puts "PASS: debug level setting"
|
||||
|
||||
# Higher debug levels
|
||||
sta::set_debug "search" 3
|
||||
sta::set_debug "search" 0
|
||||
sta::set_debug "graph" 3
|
||||
sta::set_debug "graph" 0
|
||||
puts "PASS: higher debug levels"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 9: Format functions
|
||||
# Exercises: format_time, format_capacitance, format_resistance, etc.
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 9: format functions ---"
|
||||
|
||||
# Time formatting
|
||||
foreach t {1e-9 1e-10 1e-11 1e-12 5.5e-9 0.0} {
|
||||
set ft [sta::format_time $t 4]
|
||||
puts "format_time($t) = $ft"
|
||||
}
|
||||
|
||||
# Capacitance formatting
|
||||
foreach c {1e-12 1e-13 1e-14 1e-15 5.5e-12 0.0} {
|
||||
set fc [sta::format_capacitance $c 4]
|
||||
puts "format_capacitance($c) = $fc"
|
||||
}
|
||||
|
||||
# Resistance formatting
|
||||
foreach r {100 1000 10000 0.1 0.0} {
|
||||
set fr [sta::format_resistance $r 4]
|
||||
puts "format_resistance($r) = $fr"
|
||||
}
|
||||
|
||||
# Power formatting
|
||||
foreach p {1e-3 1e-6 1e-9 5.5e-3 0.0} {
|
||||
set fp [sta::format_power $p 4]
|
||||
puts "format_power($p) = $fp"
|
||||
}
|
||||
|
||||
puts "PASS: format functions"
|
||||
|
||||
puts "ALL PASSED"
|
||||
Reference in New Issue
Block a user